Abstract: A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer.

Abstract: A method of suppressing junction capacitance of the source/drain regions is disclosed in this invention. The source/drain regions are formed by double implantation of phosphorus ions and arsenic ions. The phosphorus ion implantation lowers the energy needed in the implantation of arsenic ions, and reduces dislocations in the source/drain regions formed during implanting arsenic ions. Further, the double implantation suppresses the junction profile of arsenic ions, and enhances the width of depletion regions. So, the junction capacitance is reduced, thereby accelerate the function of semiconductor devices.

Abstract: A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Abstract: A rotary switch has a rotary dial, an operation shaft, a housing, a rotary plate and a circuit board. A binding member extends from the rotary dial and inserts through a central through hole of the housing and connects to the contact plate to allow the rotary dial and the contact plate to rotate together. The housing and the circuit board attach and remain stationary, independent of any rotational movement of the rotary dial. The contact plate has a plurality of contact protrusions that extend in a predetermined pattern so that in accordance with rotation of the rotary dial, at least one contact protrusion is brought into electrical contact with at least one linear contact member belonging to a contact member array positioned on the circuit board.

Abstract: A switch for selectively supplying power or signals from a fixed first conductive pin to fixed second and third conductive pins includes a housing, a pushbutton unit including a tappet situated in the housing, a conductive unit including the first, second, and third conductive pins, and a switching unit including a conductive sway element for respectively selectively connecting the first conductive pin to either the second or the third conductive pin. The switching unit also includes an elastic element coupled at a first end with the tappet and at a second end the sway element such that when the first end of the elastic clement is in a first position, said elastic element causes the sway element to connect said first and third conductive pins, and when the first end of the elastic element is moved past a critical line to a second position, the elastic element causes the sway element to also move past the critical line and connect the first and second conductive pins.

Abstract: A droplet proof keyboard for notebook computer comprises a base; a circuit membrane set on the base; a mounting plate on the circuit membrane set and having a through hole and a plurality of retaining parts for each keyswitch; a rubber cone set having a plurality of rubber cones, each rubber cone having a press part passing the through hole and touching the circuit membrane when the keyswitch is pressed; a plurality of key caps each corresponding to a keyswitch and having locking parts on lower surface thereof; an opaque plate arranged on the mounting plate and clamping the rubber cone; the opaque plate having an opening for each rubber cone and a plurality of slits through which lower ends of a switching lever passing; a switching lever set having a plurality of switching levers; each switching lever having a plurality of upper ends pivotally arranged on the locking parts of the keycap and a plurality of lower ends pivotally arranged on the retaining parts of the mounting plate.

Abstract: An adapter with diversified plugs and rectifying function. The adapter including a casing and a pivotally jointed cover. A penetration-disposing portion in a vacant lot of the casing is defined by a plurality of partition portions for setting differently sized plug pins. The adapter includes internally hollowed auxiliary pins or conductive members. In an outer rim of each of the partition portions, a first snap-retaining section is formed in association with an outer rim of the auxiliary pins or the plug pins. A circuit coupled with an external power cord and two conductive units connected to the circuit are built in the cover. One end of the conductive members can be depressed to contact an arbitrary set of the plug pins, and after the cover is closed, the conductive units are depressed to contact the conductive members to force the plug pins to be exposed through the penetration-disposing portions for coupling with an external power source.

Abstract: A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core.

Abstract: A rotary switch has a rotary dial, an operation shaft, a housing, a rotary plate and a circuit board. A binding member extends from the rotary dial and inserts through a central through hole of the housing and connects to the contact plate to allow the rotary dial and the contact plate to rotate together. The housing and the circuit board attach and remain stationary, independent of any rotational movement of the rotary dial. The contact plate has a plurality of contact protrusions that extend in a predetermined pattern so that in accordance with rotation of the rotary dial, at least one contact protrusion is brought into electrical contact with at least one linear contact member belonging to a contact member array positioned on the circuit board. The rotary switch operates when a shaft contact portion mounted on the circuit board is pressed by a lower end of the operation shaft in accordance with axial movement of the operation shaft.

Abstract: A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Abstract: A low-noise fan-filter unit for providing filtered airflow is disclosed. The fan-filter unit includes a housing having at least an air inlet and a coaxial air outlet; a centrifugal fan installed in the housing for drawing air into the housing and propelling it out of the air outlet; a filter installed between the fan and the air outlet for removing impurities from the air; and a noise reduction arrangement installed between the fan and the filter for reducing noise. The noise reduction arrangements includes three parting plates incorporating with the housing to form a tortuous air passageway which U-turns the airflow at least two times. The tortuous and extended air passageway, and some sound-absorbing materials furnished along the air passageway increase the contact area between the airflow and the sound-absorbing materials, and enhance the effect of noise absorption.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes a semiconductor substrate which is provided and forms a gate oxide layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, pattern transfers onto the photoresist layer after going through an exposure and a development. Furthermore, the gate layer and the gate oxide layer are then etched by using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin nitride oxide (NO, N2O) layer is grown by utilizing rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN). Hereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A TEOS layer and a silicon nitride layer are deposited by using LPCVD, and forming spacers by etching the silicon nitride layer and the TEOS layer.

Abstract: A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.

Abstract: An improved foldable pushbutton-input device conformable to human body mechanism, wherein a plurality of assembly-jointing sections is defined by a plurality of properly spaced predetermined cutting lines on a baseboard; a circuit board made of a flexible material having a plurality of pushbutton-input circuit sections in positions corresponding with the assembly-jointing sections and also defined by the same cutting lines is attached on the baseboard; a signal-output circuit section is formed by extending the lateral edges of the pushbutton-input circuit sections and connected therewith; and a plurality of amount predetermined key sets is disposed on the circuit board or on the baseboard in virtue of the division cutting lines to thereby construct the foldable pushbutton-input device with a considerably reduced volume.

Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.

Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.