Patents by Inventor Wen Fang

Wen Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190098883
    Abstract: Disclosed is a multi-angled fishing hook (1) that includes multiple unclosed angles (2) with a plurality of grooves (3) forming into the entire bend (4) of the hook. The multiple unclosed angles include at least 4-6 regular or irregular more than 90 degrees of angles distributed separately along the bend. The plurality of grooves is cut transversely to each straight line of the angles on the bend. The bend of the hook that connects the sharp point (5) to the shank (6) is therefore an obvious regular or irregular multi-angled shape (7). The multi-angled fishing hook is to utilise the compressive force as well as friction that develop from each formed angle with grooves to grip bait more tightly and securely on the bend of the hook so that the movements of bait and caught fish are restricted and unable to fall off or escape easily.
    Type: Application
    Filed: September 1, 2018
    Publication date: April 4, 2019
    Inventors: Wen-Fang Carrie Tung, Johannes Georg Meierhofer
  • Publication number: 20190103460
    Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Chia-Lin Wang, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Publication number: 20190067543
    Abstract: A heat dissipation substrate structure includes a multilayer circuit board including a core board and build-up boards, a heat conduction layer, a cavity structure, bonding pads, and vias. The heat conduction layer is disposed within the core board, or on a surface of the core board, or on a surface of one of the build-up boards. The cavity structure is in the multilayer circuit board with respect to the heat conduction layer and exposes a first surface of the heat conduction layer. The bonding pads are on the surface of the multilayer circuit board at a side of a second surface of the heat conduction layer. The portions of the vias are connected to portions of the bonding pads and the heat conduction layer. Accordingly, heat flow can be distributed via a heat dissipation path from the bonding pads through the vias to the heat conduction layer.
    Type: Application
    Filed: November 30, 2017
    Publication date: February 28, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Wen-Fang Liu, Shao-Chien Lee, Chen-Wei Tseng, Zong-Hua Li
  • Publication number: 20190067880
    Abstract: An electrical connector includes an insulative housing enclosed within a metallic shell wherein the housing forms a mating cavity and the shell includes a first shell and a second shell assembled together. The first shell includes a main body abutting against the housing, and a folded plate abutting against the main body and having a plurality of first spring tangs for engagement with the case in which the connector is position. The folded plate forms a securing tab and the housing includes a retention slot receiving the securing tab therein so as to prevent outward movement of the folded plate in the vertical direction.
    Type: Application
    Filed: August 31, 2018
    Publication date: February 28, 2019
    Inventors: WEN-FANG ZHANG, WEI ZHONG, JIAN-KUANG ZHU
  • Patent number: 10204996
    Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang
  • Publication number: 20190044272
    Abstract: An electrical connector includes a contact module integrally enclosed within an insulative outer cover via an over-molding process. The outer cover includes a base and a mating tongue extending from the base. The mating tongue includes a pair of mating surfaces. The contact module includes a body located in the base and the extension extending from the body and located within the mating tongue. The body forms at least one positioning hole through which the core pin of the over-molding mold extends. The positioning hole is dimensioned/configured to have the corresponding core pin snugly restrained in the first horizontal direction while loosely confined in the second horizontal direction perpendicular to the first horizontal direction.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 7, 2019
    Inventors: WEN-FANG ZHANG, WEI ZHONG, JIAN-KUANG ZHU
  • Publication number: 20190019001
    Abstract: A fingerprint identification system includes: a fingerprint sensing circuit having a power supply terminal and a floating ground terminal, used for generating a first signal; and a signal generation circuit having a first output terminal and a second output terminal, wherein the first output terminal is coupled to the power supply terminal, and the second output terminal is coupled to the floating ground terminal, the signal generation circuit is used for generating a floating power signal to the power supply terminal according to the first signal, and for generating a floating ground signal to the floating ground terminal according to the first signal, wherein the floating power signal has a floating power amplitude, and the floating ground signal has a floating ground amplitude; and wherein the signal generation circuit has a breakdown voltage, and both the floating power amplitude and the floating ground amplitude are greater than the breakdown voltage.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: HSIN-WEN FANG, YU-AN LIANG, MENG-TA YANG
  • Publication number: 20190012506
    Abstract: A fingerprint identification system is provided, which includes: a plurality of first pixel circuits; a first sensing circuit for outputting a first output signal; at least one second pixel circuit; a second sensing circuit for outputting a second output signal, wherein the second sensing circuit includes a second integration circuit having a second integral input terminal; a second calibration circuit coupled to the second integral input terminal; a third calibration circuit coupled to the second integral input terminal, wherein the second calibration circuit and the third calibration circuit are used for calibrating the second output signal; and a differential amplifier circuit coupled to the first sensing circuit and the second sensing circuit and used for generating an amplified output signal.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: HSIN-WEN FANG, KUO-HAO CHAO
  • Patent number: 10168847
    Abstract: A processing system comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, wherein the sensing module is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism configured to couple with a second sensor electrode path and configured to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and wherein the selectable current source is enabled during acquisition of the test signal output. The determination module configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 1, 2019
    Assignee: Synaptics Incorporated
    Inventors: Jorge Saucedo, John M. Weinerth, Wen Fang
  • Publication number: 20180368263
    Abstract: A chip package circuit board module including a circuit board and at least one original chip is provided. The circuit board includes at least one first pad, at least one second pad and at least one substitute pad. The at least one second pad is located besides the at least one first pad and separated from the at least one first pad. The at least one substitute pad is adjacent to the at least one second pad and separated from the at least one first pad and the at least one second pad. The at least one original chip is connected to the at least one first pad and at least one the second pad, respectively. A total width of a portion corresponding to each of the at least one second pad and a portion corresponding to the substitute pad adjacent to the second pad of the first pad is greater than or equal to twice a width of the original chip.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Applicant: Unimicron Technology Corp.
    Inventors: Wen-Fang Liu, Shao-Chien Lee, Chen-Wei Tseng, Zong-Hua Li, Chien-Tsai Li
  • Patent number: 10159151
    Abstract: A chip package circuit board module including a circuit board and at least one original chip is provided. The circuit board includes at least one first pad, at least one second pad and at least one substitute pad. The at least one second pad is located besides the at least one first pad and separated from the at least one first pad. The at least one substitute pad is adjacent to the at least one second pad and separated from the at least one first pad and the at least one second pad. The at least one original chip is connected to the at least one first pad and at least one the second pad, respectively. A total width of a portion corresponding to each of the at least one second pad and a portion corresponding to the substitute pad adjacent to the second pad of the first pad is greater than or equal to twice a width of the original chip.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 18, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Fang Liu, Shao-Chien Lee, Chen-Wei Tseng, Zong-Hua Li, Chien-Tsai Li
  • Publication number: 20180357458
    Abstract: A capacitive sensing system is provided, which includes: a pixel matrix for sensing a plurality of voltage variations generated by pressing of a fingerprint; and a calibration unit coupled to the pixel matrix and used for calibrating the plurality of voltage variation of the pixel matrix according to a control signal generated based on the plurality of voltage variations. The capacitive sensing system according to the present disclosure has advantages of improving the consistency of the voltage variations detected by the pixel units and reducing the occurrence of distortion.
    Type: Application
    Filed: August 16, 2018
    Publication date: December 13, 2018
    Inventors: HSIN-WEN FANG, MENG-TA YANG
  • Patent number: 10148029
    Abstract: An electrical connector includes an insulative housing, a plurality of terminals retained in the housing. The housing includes a base and a mating tongue extending forwardly from the base. The mating tongue forms opposite mating surfaces extending forwardly and vertically converging toward each other. The terminal includes a front contacting section, a middle retaining section rearwardly extending from the front contacting section, and a rear soldering section extending rearwardly from the middle retaining section. The front contacting section has two contacting faces respectively exposed upon the opposite mating surfaces of the mating tongue. Each terminal is made via stamping sheet metal and extends in a plane with a through hole in the front contacting section.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 4, 2018
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Xiao-Xian Tian, Jian-Kuang Zhu, Wen-Fang Zhang
  • Patent number: 10141398
    Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Chin-Chia Kuo, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10133288
    Abstract: An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 20, 2018
    Assignee: Synopsys, Inc.
    Inventors: Wen Fang, Chinh Vo
  • Publication number: 20180317538
    Abstract: A roasting drum has a main body and at least one opening formed through the main body. The main body has a first end, a second end opposite the first end, and multiple drums. The multiple drums are mounted around one another in sequence, are fastened to one another, and communicate with one another. Each one of the multiple drums has a blending blade formed on an inner surface of the drum. The blending blade is spiral and extends from the first end toward the second end. The blending blade of one of the multiple drums twists along a clockwise direction from the first end toward the second end. The blending blade of another one of the multiple drums that is mounted around the drum twists along a counter-clockwise direction from the first end toward the second end.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 8, 2018
    Inventor: Wen-Fang CHANG
  • Publication number: 20180315776
    Abstract: A display device includes a first substrate and a flexible circuit board. Data lines, scan lines, thin film transistors, gate contacts, and source contacts are disposed on the first substrate. The scan lines are intersected with the data lines. The thin film transistors are respectively connected to the data lines and the scan lines. The gate contacts are connected to the scan lines. The source contacts are connected to the data lines. The display device further includes first conductive patterns disposed on a side of the first substrate, and the first conductive patterns are connected to at least some of the gate contacts on the side of the first substrate. First pads of the flexible circuit board are connected to the first conductive patterns.
    Type: Application
    Filed: March 16, 2018
    Publication date: November 1, 2018
    Inventors: Hao-An CHUANG, Wen-Fang SUNG
  • Publication number: 20180295723
    Abstract: A manufacturing method of a circuit board structure includes the following steps: providing an inner circuit structure which includes a core layer; performing a build-up process to laminate a first build-up circuit structure on a first patterned circuit layer of the inner circuit structure, wherein the first build-up circuit structure includes an inner dielectric layer, and the inner dielectric layer directly covers an upper surface of the core layer and the first patterned circuit layer; removing a portion of the first build-up circuit structure to form an opening extending from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion of the inner dielectric layer; performing a sandblasting process on a first inner surface of the inner dielectric layer exposed by the opening to at least remove the portion of the inner dielectric layer exposed by the opening.
    Type: Application
    Filed: June 14, 2018
    Publication date: October 11, 2018
    Applicant: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Wen-Fang Liu
  • Patent number: 10084083
    Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 25, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: D845905
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: April 16, 2019
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Wen-Fang Zhang, Jian-Kuang Zhu, Chun-Sheng Li