Abstract: An electrical connector includes an insulative cover enclosing the terminal module via an overmolding process. The cover includes a base and a tongue portion extending forwardly from the base and forming opposite mating surfaces thereon. The terminal module includes a plurality of terminals retained in the insulator wherein a contacting section of the terminal is exposed upon the mating surface. A pair of reinforcing metal plates are disposed upon the terminal module and enclosed by said cover except front portions of said reinforcing metal plates exposed outside of the cover.

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

Abstract: A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.

Abstract: The present invention provides a heart murmur detection device. The heart murmur detection device includes: an ECG signal detection unit for detecting an ECG signal from a heart of a user; a heart beat detection unit for detecting the frequency of the ECG signal; a plurality of sound receiving units for receiving a plurality of sound signals from the heart of the user; a signal transforming unit for transforming the sound signals into a plurality of electric phonic signals, and for retrieving the electric phonic signals on the basis of the ECG signal; and a signal processing unit for determining a heart murmur generating position. Moreover, the present invention further provides a heart murmur detection method.

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

Abstract: Provided are an operation control method for a touchscreen terminal and a mobile terminal. The method includes: a mobile terminal entering into an operation type locked state under a specified condition; and after detecting a specified type of operation, the mobile terminal prohibiting any response to the specified type of operation. With the embodiments of the present document, it is to enable the user, when using the mobile terminal, to not only obtain the same effect of preventing incorrect touch or operation as that of screen locking, but also not to be blocked by an unnecessary locked screen interface when needing to read the contents in the standby interface, thus simplifying the user operation, and enhancing the operation experience of the mobile terminal.

Abstract: A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.

Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

Abstract: Bandgap Voltage Reference circuits configured to produce reference voltages with both voltage offset and a voltage temperature slope are disclosed. By generating the voltage offset from a temperature-independent current, the voltage offset of the reference voltage may be temperature-independent, while generating the voltage temperature slope from a temperature-dependent current allows the voltage temperature slope to vary with temperature. To ensure that the voltage offset remains independent from the voltage temperature slope, an apparatus is disclosed for orthogonal trimming of voltage offset and voltage temperature slope.

Abstract: A transparent stereo display includes a first substrate, a second substrate, a common electrode, a display medium, and a patterned phase retardation film. A plurality of pixel structures is disposed on the first substrate. The pixel structures include a plurality of right eye pixel structures and left eye pixel structures. Each pixel structure includes a display region, a first region, and a second region. The patterned phase retardation film includes right eye polarized patterns and left eye polarized patterns. The right eye polarized patterns are disposed corresponding to the right eye pixel structures, and the left eye polarized patterns are disposed corresponding to the left eye polarized patterns. An edge of each right eye polarized pattern overlaps with the second region of the corresponding right eye pixel structure. An edge of each left eye polarized pattern overlaps with the second region of the corresponding left eye pixel structure.

Abstract: Provided in the embodiments of the present disclosure are a file transmission method and apparatus, a terminal, a wearable device and a computer storage medium. The method includes: detecting whether an automatic file transmission condition is satisfied between a first electronic device and a second electronic device to obtain a first detection result; and when the first detection result is used for representing that the automatic file transmission condition is satisfied between the first electronic device and the second electronic device, selecting a first file having a preset file attribute and transmitting the first file.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

Abstract: A spirit level has a base ruler having a hollow chamber and a leveling bubble unit. The leveling bubble unit includes a bubble tube, a bubble tube base and a fixing base. The fixing base has a limit slot for the bubble tube base. The position on the base ruler where the leveling bubble unit is configured has an inlaying opening. The fixing base of the leveling bubble unit is hidden inside the hollow chamber in a sinking style, such that, when the fixing base is placed into the hollow chamber, the tip end of the fixing base is held inside the inlaying opening. The two sides of the top of the fixing base are respectively configured with elastic clasps, and the tip end of the elastic clasp has a slant resisting surface to resist against the corner of the inner wall of the inlaying opening.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.