Patents by Inventor Wen-hao Cheng

Wen-hao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • USB INTEGRATED CIRCUIT
    Publication number: 20210064558
    Abstract: A USB integrated circuit includes three TX connecting component pairs and three RX connecting component pairs. The first TX connecting component pair and the first RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of the first USB connector. The second TX connecting component pair and the second RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of a second USB connector. The third TX connecting component pair is coupled to the second TX pin pair of the first USB connector or to the second TX pin pair of the second USB connector. The third RX connecting component pair is coupled to the second RX pin pair of the first USB connector or to the second RX pin pair of the second USB connector.
    Type: Application
    Filed: October 24, 2019
    Publication date: March 4, 2021
    Applicant: VIA LABS, INC.
    Inventors: Wen-Yu Tseng, Wen-Hao Cheng, Terrance Shiyang Shih
  • Redistribution layer metallic structure and method
    Patent number: 10916517
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • Apparatus and a Method of Forming a Particle Shield
    Publication number: 20210018853
    Abstract: A lithography system includes a radiation source and a photomask. The radiation source is configured to generate electromagnetic radiation traveling towards the photomask. The lithography system also includes an incident channel between the radiation source and the photomask for the electromagnetic radiation to travel through. There are a first injection nozzle configured to generate a first particle shield between the photomask and an exit port of the incident channel and a second injection nozzle configured to generate a second particle shield inside the incident channel.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 21, 2021
    Inventor: Wen-Hao Cheng
  • HIERARCHICAL DENSITY UNIFORMIZATION FOR SEMICONDUCTOR FEATURE SURFACE PLANARIZATION
    Publication number: 20210019465
    Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.
    Type: Application
    Filed: March 2, 2020
    Publication date: January 21, 2021
    Inventors: Venkata Sripathi Sasanka Pratapa, Jyun-Hong Chen, Wen-Hao Cheng
  • SEMICONDUCTOR WAFER MEASUREMENT METHOD AND SYSTEM
    Publication number: 20200364844
    Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
  • Apparatus and a method of forming a particle shield
    Patent number: 10788764
    Abstract: An apparatus for generating a laminar flow includes an injection nozzle and a suction nozzle. The injection nozzle and the suction nozzle are operable to form the laminar flow for blocking particles from contacting a proximate surface of an object. The injection nozzle includes a main outlet to blow out the laminar flow. The injection nozzle is configured to generate a Coanda flow along an external surface of the injection nozzle. The suction nozzle is configured to provide a gas pressure gradient for the laminar flow.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Hao Cheng, Chue San Yoo, Ching-Yueh Chen
  • Semiconductor wafer measurement method and system
    Patent number: 10762621
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Redistribution layer metallic structure and method
    Patent number: 10658315
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • Redistribution Layer Metallic Structure and Method
    Publication number: 20200144208
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Application
    Filed: December 26, 2019
    Publication date: May 7, 2020
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • EXTREME ULTRAVIOLET LIGHT REFLECTIVE STRUCTURE INCLUDING NANO-LATTICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200133112
    Abstract: An EUV reflective structure includes a substrate and multiple pairs of a Si layer and a Mo layer. The Si layer includes a plurality of cavities.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 30, 2020
    Inventors: Benny KU, Keith Kuang-Kuo KOAI, Wen-Hao CHENG
  • SYSTEMS AND METHODS FOR SYSTEMATIC PHYSICAL FAILURE ANALYSIS (PFA) FAULT LOCALIZATION
    Publication number: 20200133959
    Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.
    Type: Application
    Filed: July 31, 2019
    Publication date: April 30, 2020
    Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20200075518
    Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.
    Type: Application
    Filed: June 3, 2019
    Publication date: March 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hao CHENG, Yen-Yu CHEN, Chih-Wei LIN, Yi-Ming DAI
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND ASSOCIATED SEMICONDUCTOR DIE
    Publication number: 20200020655
    Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.
    Type: Application
    Filed: March 14, 2019
    Publication date: January 16, 2020
    Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
  • Redistribution Layer Metallic Structure and Method
    Publication number: 20190304939
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • SEMICONDUCTOR WAFER MEASUREMENT METHOD AND SYSTEM
    Publication number: 20190259140
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
  • Bonding pad process with protective layer
    Patent number: 10354965
    Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Sheng-Wei Yeh, Yen-Yu Chen, Chih-Wei Lin, Wen-Hao Cheng
  • Method and system for diagnosing a semiconductor wafer
    Patent number: 10304178
    Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANFACTURING COMPANY, LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Bonding Pad Process with Protective Layer
    Publication number: 20190096834
    Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih Wei BIH, Chun-Chih LIN, Sheng-Wei YEH, Yen-Yu CHEN, Chih-Wei LIN, Wen-Hao CHENG
  • Apparatus and a Method of Forming a Particle Shield
    Publication number: 20190094719
    Abstract: An apparatus for generating a laminar flow includes an injection nozzle and a suction nozzle. The injection nozzle and the suction nozzle are operable to form the laminar flow for blocking particles from contacting a proximate surface of an object. The injection nozzle includes a main outlet to blow out the laminar flow. The injection nozzle is configured to generate a Coanda flow along an external surface of the injection nozzle. The suction nozzle is configured to provide a gas pressure gradient for the laminar flow.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 28, 2019
    Inventors: Wen-Hao Cheng, Chue San Yoo, Ching-Yueh Chen
  • Apparatus and a method of forming a particle shield
    Patent number: 10168626
    Abstract: An apparatus for generating at least one particle shield. The at least one particle shield includes a first component and a second component. The first component and the second component are usable to form a first particle shield of the at least one particle shield for blocking particles from contacting a proximate surface of an object, the first particle shield is substantially parallel to and physically separated from the proximate surface of the object, and the first particle shield includes an energy gradient force or a velocity gradient force.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chue San Yoo, Ching-Yueh Chen, Wen-Hao Cheng