Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A light-detection method for a light-detection device including a plurality of scan lines, a plurality of read-out lines and a plurality of photo sensing elements is provided. Each of the plurality of photo sensing elements is coupled to one of the plurality of scan lines and one of the plurality of read-out lines. The method includes simultaneously turning on at least two of the plurality of scan lines to turn on a portion of the plurality of photo sensing elements which are coupled to the turned-on scan lines, turning on at least one of the plurality of read-out lines to transmit signals of the portion of the plurality of photo sensing elements, and determining whether the signals match a trigger standard. When it is determined that the signals match the trigger standard, a reading mode is entered.

Abstract: Embodiments are provided for equalizing audio data for output by a speaker of an electronic device based on a local position or orientation of the electronic device. According to certain aspects, the electronic device can determine (858, 868) its local position based on various sensor data, and identify (870, 872) an appropriate equalization setting. In some cases, the electronic device can modify (876, 880) the equalization setting based on acoustic and/or optical data. The electronic device can apply (882) the modified or unmodified equalization setting to an audio signal and cause the speaker to output (886) the audio signal with the applied equalization setting.

Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.

Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Abstract: A data fusion based safety surveillances system has a first through Nth virtual monitoring systems and a data fusion and decision device. The data fusion and decision device defines an ith detection model of the ith virtual monitoring system, and estimates an ith detection loss probability of the ith virtual monitoring system according to detection loss sample numbers of batches of ith monitored data of the ith virtual monitoring system under conditions corresponding to the locations, batches of context data and existence of intruder, the ith detection model, the batches of ith monitored data corresponding to locations of the ith virtual monitoring system and the batches of context data. The data fusion and decision device determines a fusion parameter set according to the first through Nth detection loss probabilities, and performs data fusion on a first through Nth detection results to generate a decision result.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.

Abstract: A Hydrocarbyl Carboxybetaine represented by Formula (1) is provided: wherein, n1?0 and n2>0, A is a C1-C20 alkyl group when n1>0, and A is a single bond when n1=0.

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

Abstract: Embodiments are provided for receiving a request to output audio at a first speaker and a second speaker of an electronic device, determining that the electronic device is oriented in a portrait orientation or a landscape orientation, identifying, based on the determined orientation, a first equalization setting for the first speaker and a second equalization setting for the second speaker, providing, for output at the first speaker, a first audio signal with the first equalization setting, and providing, for output at the second speaker, a second audio signal with the second equalization setting.

Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.

Abstract: A system, including a tablet gaming table, allows casino dealers to connect with players both in-person and in Virtual Reality (VR). This system can be used for popular casino games such as blackjack or baccarat, and can also serve as a tool for casinos to increase player traffic while maximizing dealer employee efficiency.