Abstract: A system, including a tablet gaming table, allows casino dealers to connect with players both in-person and in Virtual Reality (VR). This system can be used for popular casino games such as blackjack or baccarat, and can also serve as a tool for casinos to increase player traffic while maximizing dealer employee efficiency.

Abstract: Exemplary embodiments for various via pillar structures include one or more first conductors in a first interconnect layer of a semiconductor stack interconnected with one or more second conductors in a second interconnect layer of the semiconductor stack. The one or more first conductors and/or the one or more second conductors within the first interconnect layer and the second interconnect layer, respectively, can traverse multiple directions. In some situations, this allows multiple interconnections to be utilized to interconnect the one or more first conductors and the one or more second conductors. These multiple interconnections can reduce resistance between the one or more first conductors and the one or more second conductors thereby improving performance of signals flowing between the one or more first conductors and the one or more second conductors.

Abstract: A system is includes a processor and a computer readable medium. The computer readable medium connected to the processor. The computer readable medium is configured to store instructions. The processor is configured to execute the instructions for determining, according to at least one parameter of a cell in a semiconductor device indicated by a design file, a layout pattern indicating a via pillar structure that meets an electromigration (EM) rule. The via pillar structure comprises metal layers and at least one via, and the at least one via is coupled to the metal layers. The processor is further configured to execute the instructions for including, in the design file, the layout pattern indicating the via pillar structure. The processor is further configured to execute the instructions for generating data which indicate the design file, for fabrication of the semiconductor device.

Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.

Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.

Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.

Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

Abstract: An apparatus for generating a laminar flow includes an injection nozzle and a suction nozzle. The injection nozzle and the suction nozzle are operable to form the laminar flow for blocking particles from contacting a proximate surface of an object. The injection nozzle includes a main outlet to blow out the laminar flow. The injection nozzle is configured to generate a Coanda flow along an external surface of the injection nozzle. The suction nozzle is configured to provide a gas pressure gradient for the laminar flow.

Abstract: Embodiments described herein generally related to a method for manufacturing an encapsulating structure for a display device, more particularly, for manufacturing a TFE structure including a light scattering layer. The TFE structure further includes one or more barrier layers. All layers of the TFE structure are formed in a PECVD apparatus. The light scattering layer is formed by a PECVD process, in which a silicon containing precursor and a nitrogen containing precursor are introduced into the PECVD apparatus. The flow rate of the silicon containing precursor is equal to or greater than the flow rate of the nitrogen containing precursor. The light scattering layer enhances light out-coupling from a light emitting device disposed under the TFE structure.

Abstract: A light source module of a projector includes a light source having a lamp axis, a fan for providing a cooling airflow, and a flow guide device disposed between the light source and the fan and for guiding the cooling airflow. The flow guide device includes a first air channel connected between a side of the light source and an air outlet of the fan, a second air channel connected between another side of the light source and the air outlet of the fan, and a first airflow control assembly disposed in the first air channel and for controlling the first air channel either in communication or non-communication states via gravity. The first airflow control assembly has a first control rotating shaft inclined relative to the lamp axis and a first included angle between the first control rotating shaft and the lamp axis is less than 90 degrees.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.

Abstract: A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

Abstract: A light source module includes a light source having an optical axis, a fan for providing a cooling airflow and a deflector disposed between the light source and the fan and directing a flowing direction of the cooling airflow. The deflector includes a first air duct connected between a first side of the light source and an air outlet of the fan, a second air duct connected between a second side of the light source and the air outlet of the fan, and a first airflow control assembly controlling the first air duct in a communicating state or a non-communicating state and having a first control shaft and a first airflow passing portion rotating about the first control shaft. The first control shaft is inclined to the optical axis so that a first angle is formed therebetween. The first angle is between 0 and 90 degrees.

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.

Abstract: A method for performing multi-camera automatic patrol control with aid of statistics data in a surveillance system and an associated apparatus are provided. The method includes: utilizing any camera of a plurality of cameras to capture a plurality of reference images along a plurality of capturing directions of the camera, and performing image analysis operations on the reference images to generate statistics data; performing importance estimation operations according to the statistics data to generate a plurality of importance estimation values respectively corresponding to the capturing directions; selecting one of the capturing directions as a predetermined scheduling direction of the camera according to the importance estimation values; and during a time interval of a plurality of time intervals of a scheduling plan, controlling the camera to capture a series of images along the predetermined scheduling direction to monitor the predetermined scheduling direction.

Abstract: A display is provided. The display includes a display panel and a timing controller. The timing controller controls the images displayed on the display panel according to a display driving signal from a host and the display driving configuration of the display panel. The timing controller determines whether there is an error in the display driving signal, and calculates an error count. The timing controller determines whether the error count is lower than a predetermined threshold. If so, the timing controller controls the display panel to display the display images normally according to the display driving signal. If not, the timing controller reports a display error signal to the host, so that the host dynamically updates the display driving configuration.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.