Patents by Inventor Wen Hao

Wen Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170323047
    Abstract: The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 9, 2017
    Inventors: Meng-Kai HSU, Yuan-Te Hou, Wen-Hao Chen
  • Publication number: 20170323046
    Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 9, 2017
    Inventors: Meng-Kai HSU, Yuan-Te Hou, Wen-Hao Chen
  • Patent number: 9812052
    Abstract: A 2D/3D image displaying apparatus includes a sub-pixel, a first and second data lines and a gamma circuit. The sub-pixel includes a first portion and a second portion. The first and second data lines are coupled to the first and second portion of the sub-pixel, respectively. The gamma circuit transmits correlated gamma signals to a driving circuit for driving the first and second part of the sub-pixel via the first and second data lines when 2D image is to be displayed, and transmits a single gamma signal to the driving circuit for driving the first and second portion of the sub-pixel via the first and second data lines when 3D image is to be displayed.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: November 7, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chao-Yuan Chen, Wen-Hao Hsu, Ting-Jui Chang
  • Publication number: 20170317027
    Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Kam-Tou Sio, Pin-Dai Sue, Ru-Gun Liu, Shi-Wei Peng, Wen-Hao Chen, Yung-Sung Yen, Chun-Kuang Chen
  • Patent number: 9799602
    Abstract: An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang-Hung Chang, Wen-Hao Chen, Yuan-Te Hou, Kumar Lalgudi
  • Patent number: 9798395
    Abstract: An electronic control apparatus including motion sensors is integrated in a portable electronic device to responsively control a media content stored in the portable electronic device, in response to motion sensor signals to flip, zoom, displace images/pages of the media content displayed on a display field of a display thereof. Accordingly, a responsive control method includes the steps of: presetting a first threshold angle; sensing an first rotation angle of the portable electronic device to send out a first rotation sensing signal as a rotation of a yaw, pitch or roll of a portable electronic device detected by a sensing module including motion sensors; and receiving the first rotation sensing signal to calculate and determine whether the first rotation angle is greater than the first threshold angle to responsively control a media content stored in an electronic control apparatus be flipped, zoomed or displaced when the first rotation angle is greater than the first threshold angle.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: October 24, 2017
    Assignee: CM HK LIMITED
    Inventors: Zhou Ye, Shun-Nan Liou, Ying-Ko Lu, Wen-Hao Chang, Tigran Tadevosyan
  • Patent number: 9792993
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 17, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Patent number: 9787966
    Abstract: A method and device for coding interlaced video data. The method includes coding interlaced video data captured from a plurality of different positions, the interlaced video data including data for a top field and a bottom field for at least one interlaced video scan, the top field including every other line starting with a top line of a frame and the bottom field including interposed lines in the frame.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 10, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Fang-Chu Chen, Ching-Chieh Lin, Wen-Hao Chung
  • Patent number: 9785738
    Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Charles Jay Alpert, Zhuo Li, Wing Kai Chow, Wen-Hao Liu, Derong Liu
  • Patent number: 9768119
    Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yeh Yu, Yuan-Te Hou, Chung-Min Fu, Wen-Hao Chen, Wan-Yu Lo
  • Publication number: 20170255740
    Abstract: A method is disclosed that includes determining whether there is a conflict graph representing that each spacing between any two of at least five adjacent patterns of multiple-patterning patterns of a layout of an integrated circuit (IC) is less than a threshold spacing, and if there is the conflict graph, modifying the multiple-patterning patterns to exclude patterns represented by the conflict graph, for fabrication of the IC.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 7, 2017
    Inventors: Meng-Kai HSU, Yuan-Te HOU, Wen-Hao CHEN
  • Publication number: 20170250370
    Abstract: Embodiments of the disclosure provide interface integration and adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of enhancing interface adhesion and integration in a film structure disposed on a substrate includes performing a plasma treatment process on an inorganic layer disposed on a substrate in a processing chamber to form a treated layer on the substrate, wherein the substrate includes an OLED structure, controlling a substrate temperature less than about 100 degrees Celsius, and forming an organic layer on the treated layer. Furthermore, an encapsulating structure for OLED applications includes an inorganic layer formed on an OLED structure on a substrate, an electron beam treated layer formed on the inorganic layer, and an organic layer formed on the electron beam treated layer.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Inventors: Jrjyan Jerry CHEN, Soo Young CHOI, Helinda NOMINANDA, Wen-Hao WU
  • Patent number: 9740540
    Abstract: A process context-awareness method analyzes events arising from a process according to context concepts, compare and analyze entity contents of the events, event types, applicable contextual situations and rules, so as to subsequently trigger the other activities or yield result. The method applies to enterprise information systems, project scheme execution or meets any other operation requirement, suits different enterprise operational context, gains insight into dynamic circumstances of the enterprise context.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: August 22, 2017
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Tzu-Ming Chan, Wen-Hao Hsiao
  • Patent number: 9731296
    Abstract: A biochemical reactor includes a temperature control device containing a substrate, a first conductive layer, a second conductive layer, a receiving hole, and a heating element. The substrate has a through hole for accommodating the vessel; the receiving hole is adjacent to the through hole for receiving the heating element; the first conductive layer has a connecting region formed on the wall of the through hole; and two terminals of the heating element are respectively connected electrically to the first and the second conductive layers. As such, the heat generated from the heating element can be transferred to the through hole via the first conductive layer to heat the vessel.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 15, 2017
    Assignee: GENEREACH BIOTECHNOLOGY CORP.
    Inventors: Chen Su, Hsiao-Fen Chang, Pei-Yu Li, Yun-Lung Tsai, Ching-Ko Lin, Wen-Hao Cheng
  • Publication number: 20170228944
    Abstract: A method for billing of a parking fee includes the steps of: when it is determined that neither license plate identifier data nor time data is stored in a storage unit, that no target is contained in a current image, and that a license plate identifier is recognized in the current image, storing time at which the current image is captured and the license plate identifier in the storage unit to respectively serve as the time data and the license plate identifier data; and when it is determined that the license plate identifier data and the time data are stored, and that the license plate identifier is recognized, calculating a parking fee of the vehicle according to a parking rate, the time data, and the time at which the current image is captured.
    Type: Application
    Filed: August 23, 2016
    Publication date: August 10, 2017
    Inventors: Kung-Ming LAN, Wen-Hao WANG, Ching-Tien LIN
  • Publication number: 20170225318
    Abstract: A ratchet wrench includes a first room, a second room, an engaging portion, a third room and a first groove in the function end thereof. Multiple ratchet wheels are received in the third room and one of which is rotatably received in the first room. Each ratchet wheel includes a first pivotal portion, a second pivotal portion and a first toothed portion which is defined in a curved and concaved manner in the outer periphery of the ratchet wheel. A pawl is located in the second room and has a second toothed portion which is engaged with the first toothed portion of the ratchet wheel. The distance defined between the deepest point of the first toothed portion to the first pivotal portion or the second pivotal portion is larger than the distance that the ratchet wheel shifts relative to the pawl within the first room.
    Type: Application
    Filed: May 17, 2016
    Publication date: August 10, 2017
    Inventors: TSAN-LUNG CHEN, WEN-HAO YU, KA-CHUNG HO
  • Publication number: 20170206969
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Application
    Filed: January 16, 2017
    Publication date: July 20, 2017
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Publication number: 20170207772
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Publication number: 20170206968
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Application
    Filed: November 16, 2016
    Publication date: July 20, 2017
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Publication number: 20170199471
    Abstract: The present disclosure provides an apparatus. The apparatus comprises a field generator, configured to produce a field shield protecting a reticle from foreign particles.
    Type: Application
    Filed: April 7, 2016
    Publication date: July 13, 2017
    Inventors: WEN-HAO CHENG, CHUE-SAN YOO, TSIAO-CHEN WU