Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first regions and a plurality of second regions. The first regions and the second regions are formed on the first substrate and the second substrate. In a narrow viewing mode, the luminous flux of the first regions along a first viewing direction is different from that of the first regions along a second viewing direction opposite to the first viewing direction, and the luminous flux of the second regions along the first viewing direction is substantially different from that of the first regions along the first viewing direction.

Abstract: A method is disclosed that includes: if there is a conflict graph including a sub-graph representing that each spacing between any two of three adjacent patterns of quadruple-patterning (QP) patterns in at least one of two abutting cells is smaller than a threshold spacing, performing operations including: identifying if one of edges that connect the three adjacent patterns of QP patterns to one another is constructed along, and/or in parallel with, a boundary between the two abutting cells; modifying multiple-patterning patterns of a layout of an integrated circuit (IC) to exclude patterns representing the sub-graph; and initiating generation of the IC from the modified multiple-patterning patterns, wherein at least one operation of identifying , modifying, or initiating is performed by at least one processor.

Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

Abstract: An integrated circuit (IC) structure includes a plurality of driver pins, each driver pin positioned at a driver pin level and oriented in a driver pin direction, and a plurality of layers of metal segment arrays. Each layer of metal segment arrays has a layer direction and includes two parallel metal segments oriented in the layer direction. The layer direction of a lowermost layer is perpendicular to the driver pin direction, the layer direction of each additional layer is perpendicular to the layer direction of a layer immediately below the additional layer, and each metal segment of a topmost layer is electrically connected to each driver pin of the plurality of driver pins.

Abstract: A system and method that includes receiving a layout of an integrated circuit (IC) device. A template library is provided having a plurality of parameterized shape elements. A curvilinear feature of layout is classified by selecting at least one of the parameterized shape elements that defines the curvilinear feature. A template index is associated with the layout is formed that includes the selected parameterized shape element. The template index and the layout can be delivered to a mask writer, which uses the template index and the layout to fabricate a pattern on a photomask.

Abstract: A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (MEOL) structures extending in a first direction over an active area of a substrate. The MEOL structures are interleaved between the gate structures along a second direction. The method further forms a power rail and a first metal wire extending in the second direction. The first metal wire is over the MEOL structures. A double patterning process is performed to form second and third metal wires extending in the first direction over the first metal wire and separated in the second direction. The second metal wire is cut according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the MEOL structures to the power rail.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: A system is includes a processor and a computer readable medium. The computer readable medium connected to the processor. The computer readable medium is configured to store instructions. The processor is configured to execute the instructions for determining, according to at least one parameter of a cell in a semiconductor device indicated by a design file, a layout pattern indicating a via pillar structure that meets an electromigration (EM) rule. The via pillar structure comprises metal layers and at least one via, and the at least one via is coupled to the metal layers. The processor is further configured to execute the instructions for including, in the design file, the layout pattern indicating the via pillar structure. The processor is further configured to execute the instructions for generating data which indicate the design file, for fabrication of the semiconductor device.

Abstract: Methods and system for detecting hotspots in semiconductor wafer are provided. At least one semiconductor wafer is inspected to detect a plurality of hotspots of each die in the semiconductor wafer, wherein each of the hotspots has defect coordinates in a layout of the die. The hotspots of the dies are stacked in the layout according to the defect coordinates of the hotspots. A common pattern is obtained according to the stacked hotspots corresponding to a location with specific coordinates in the layout. It is determined whether the common pattern is a known pattern having an individual identification (ID) code. A new ID code is assigned to the common pattern when the common pattern is an unknown pattern.

Abstract: A microcontroller is provided and includes a reset pin, a reset circuit, and a first logical circuit. A first reset signal is generated at the reset pin when the microcontroller is powered on. The reset circuit receives the first reset signal and generates a second reset signal. The reset circuit includes a plurality of flipflops. After the microcontroller is powered on, the reset circuit switches a state of the second reset signal according to the first reset signal when an output combination of a plurality of output values of the plurality of flipflops is not a specific value. The first logical circuit performs a first initialization operation when the state of the second reset signal is switched. When the second reset signal is switched, the reset circuit sets the output combination of the plurality of output values of the plurality of flipflops to the specific value.

Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Abstract: A ratchet wrench includes a first room, a second room, an engaging portion, a third room and a first groove in the function end thereof. Multiple ratchet wheels are received in the third room and one of which is rotatably received in the first room. Each ratchet wheel includes a first pivotal portion, a second pivotal portion and a first toothed portion which is defined in a curved and concaved manner in the outer periphery of the ratchet wheel. A pawl is located in the second room and has a second toothed portion which is engaged with the first toothed portion of the ratchet wheel. The distance defined between the deepest point of the first toothed portion to the first pivotal portion or the second pivotal portion is larger than the distance that the ratchet wheel shifts relative to the pawl within the first room.

Abstract: In examples described herein, methods for via pillar placement and an integrated circuit design including a via pillar are described. In some instances, a path within an integrated circuit or proposed integrated circuit design can be identified as having negative slack. In such instances, in particular where the path includes a fanout to input pins of receivers, a via pillar can be inserted at a location prior to fanout of the path. The via pillar can be inserted, for example, proximate to the fanout, but between the fanout and an output pin of a driver that is connected to the path.

Abstract: A method is disclosed that includes determining whether there is a conflict graph representing that each spacing between any two of at least five adjacent patterns of multiple-patterning patterns of a layout of an integrated circuit (IC) is less than a threshold spacing, and if there is the conflict graph, modifying the multiple-patterning patterns to exclude patterns represented by the conflict graph, for fabrication of the IC.

Abstract: A teaching tile set with pictorial characters thereon includes a set of tiles with pictorial characters thereon and a first Chinese character tree diagram board. The first Chinese character tree diagram board has multiple first pictorial characters thereon and multiple derived relationships among the multiple first pictorial characters, and each first pictorial character is mapped to the pictorial character on one tile of the set of tiles. The pictorial characters on the set of tiles provide modern characters that pictorize Chinese characters to simulate initial forms of ancient Chinese characters. By collaborating the teaching tile set with group games to learn derived relationships of Chinese characters, recognize Chinese characters with the same root, and distinguish components of Chinese characters, the goal of facilitating learners' understanding of the way of composing Chinese characters can be realized.

Abstract: A projection device is disposable into a display platform of a display rack having a plurality of display platforms, for directly projecting an image frame onto a projection screen of the display platform. The image frame projected to the projection screen is not reflected by any reflective mirror arranged between the projection device and the projection screen. A length of the image frame in a first direction is equal to at least ten times a length of the image frame in a second direction. Since no reflective mirror is arranged between the projection device and the projection screen, the projection device is more easily applicable to display racks.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.