Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.

Abstract: An integrated circuit (IC) structure includes a plurality of driver pins, each driver pin positioned at a driver pin level and oriented in a driver pin direction, and a plurality of layers of metal segment arrays. Each layer of metal segment arrays has a layer direction and includes two parallel metal segments oriented in the layer direction. The layer direction of a lowermost layer is perpendicular to the driver pin direction, the layer direction of each additional layer is perpendicular to the layer direction of a layer immediately below the additional layer, and each metal segment of a topmost layer is electrically connected to each driver pin of the plurality of driver pins.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (MEOL) structures extending in a first direction over an active area of a substrate. The MEOL structures are interleaved between the gate structures along a second direction. The method further forms a power rail and a first metal wire extending in the second direction. The first metal wire is over the MEOL structures. A double patterning process is performed to form second and third metal wires extending in the first direction over the first metal wire and separated in the second direction. The second metal wire is cut according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the MEOL structures to the power rail.

Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array. Each standard second array includes a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The method further includes: adding, to the M(N+Q) layer, second segments which connect corresponding first segments of the M(N+Q) metallization layer in the corresponding second standard arrays.

Abstract: An apparatus for generating at least one particle shield. The at least one particle shield includes a first component and a second component. The first component and the second component are usable to form a first particle shield of the at least one particle shield for blocking particles from contacting a proximate surface of an object, the first particle shield is substantially parallel to and physically separated from the proximate surface of the object, and the first particle shield includes an energy gradient force or a velocity gradient force.

Abstract: A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.

Abstract: The present invention relates to multi-user analytical system and corresponding device and method. The device includes an interception module configured to intercept a user's request for a first core object, wherein the first core object belongs to core object; a transformation module configured to create, in response to the request being a creation request, the first core object specific to the user; a mapping module configured to interpret, in response to the request being a non-creation request, the request as a request for the first core object specific to the user. The present invention also includes an isolation method for the multi-user analytical system. The technical solutions provided in the present invention can effectively enable multiple users to share physical resources in the analytical system, and the users are isolated from each other in a substantially transparent way.

Abstract: The present disclosure provides an apparatus. The apparatus comprises a field generator, configured to produce a field shield protecting a reticle from foreign particles.

Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first regions and a plurality of second regions. The first regions and the second regions are formed on the first substrate and the second substrate. In a narrow viewing mode, the luminous flux of the first regions along a first viewing direction is different from that of the first regions along a second viewing direction opposite to the first viewing direction, and the luminous flux of the second regions along the first viewing direction is substantially different from that of the first regions along the first viewing direction.

Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.

Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

Abstract: An apparatus for generating at least one particle shield in photolithography includes a first component and a second component. The first component and the second component are operable to form a first particle shield of the at least one particle shield for blocking particles from contacting a proximate surface of an object. The first component includes a first gas injector, and the second component includes a first gas extractor corresponding to the first gas injector. The first gas injector is configured to blow out a gas, thereby forming the first particle shield. The first gas extractor is configured to work with the first gas injector for providing gas pressure gradient for the first particle shield.

Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.

Abstract: Methods and system for detecting hotspots in semiconductor wafer are provided. At least one semiconductor wafer is inspected to detect a plurality of hotspots of each die in the semiconductor wafer, wherein each of the hotspots has defect coordinates in a layout of the die. The hotspots of the dies are stacked in the layout according to the defect coordinates of the hotspots. A common pattern is obtained according to the stacked hotspots corresponding to a location with specific coordinates in the layout. It is determined whether the common pattern is a known pattern having an individual identification (ID) code. A new ID code is assigned to the common pattern when the common pattern is an unknown pattern.

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

Abstract: The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.