Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.

Abstract: A plasma enhanced atomic layer deposition (PEALD) system used to form thin films on substrates includes a plasma chamber, a processing chamber, two or more ring units and a control piece. The plasma chamber includes an outer and an inner quartz tubular units, whose central axes are aligned with each other. Therefore, plasma is held and concentrated in an annular space formed between the outer and outer quartz tubular units. Due to the first and second through holes, the plasma flow may be more evenly distributed on most of the surface of the substrate to form evenly distributed thin films and nano particles on the substrate. In addition, due to the alignment and misalignment between the first and second through holes, the plasma generated in the plasma chamber may be swiftly allowed or disallowed to enter to the processing chamber to prevent the precursor from forming a CVD.

Abstract: A method for fixing metal onto a surface of the substrate. The present method includes steps of: providing a substrate and a mercaptoalkylsilatrane compound; dissolving the mercaptoalkylsilatrane compound in a solvent; performing a condensation reaction of the substrate with and the dissolved mercaptoalkylsilatrane compound to complete the surface modification of the substrate; and performing a covalent bonding process to metal with the mercaptoalkylsilatrane compound already modified onto the surface of the substrate to fix the metal onto the surface of the substrate.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.

Abstract: A process context-awareness method analyzes events arising from a process according to context concepts, compare and analyze entity contents of the events, event types, applicable contextual situations and rules, so as to subsequently trigger the other activities or yield result. The method applies to enterprise information systems, project scheme execution or meets any other operation requirement, suits different enterprise operational context, gains insight into dynamic circumstances of the enterprise context to thereby identify flexible solutions thereto. Hence, process information systems created with the method save manpower, time and costs otherwise incurred in constructing customized systems for use by different tenants and enhance the system maintainability.

Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

Abstract: A biochemical reactor includes a temperature control device containing a substrate, a first conductive layer, a second conductive layer, a receiving hole, and a heating element. The substrate has a through hole for accommodating the vessel; the receiving hole is adjacent to the through hole for receiving the heating element; the first conductive layer has a connecting region formed on the wall of the through hole; and two terminals of the heating element are respectively connected electrically to the first and the second conductive layers. As such, the heat generated from the heating element can be transferred to the through hole via the first conductive layer to heat the vessel.

Abstract: Embodiments relate to manipulating a multi-tenant database, wherein the multi-tenant database comprises one or more source databases for storing tenant data. An aspect includes receiving a database operation request for one or more tenant-specific logic views, wherein the tenant-specific logic views are created for respective tenants based on mapping information pointing to the one or more source databases included in the multi-tenant database and multi-tenant metadata. Another aspect includes acquiring the mapping information related to the database operation request and pointing to the one or more source databases included in the multi-tenant database. Yet another aspect includes performing a database operation corresponding to the database operation requested for the one or more source databases based on the acquired mapping information.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

Abstract: A method for forming a waferless interposer comprises the following steps. A transparent carrier is provided. A buffer layer is formed on the transparent carrier. First pads are formed on the buffer layer, and interconnections are formed on the first pads. A non-conductive layer is formed on the buffer layer and filled between adjacent the interconnections, wherein the upper surfaces of the interconnections are exposed on the non-conductive layer. A first redistribution procedure is performed to form a first conductive pattern on the non-conductive layer for connecting with the interconnections. A passivation layer is formed on the first conductive pattern, and is defined to form first contact holes thereon. Second pads are formed on the passivation layer to connect with the first conductive pattern through the first contact holes. After, a laser below the transparent carrier irradiates laser beam on the buffer layer to dissociate it for separating the interposer from the transparent carrier.

Abstract: A method, an apparatus, and a system for locating sensor data. The method includes the steps of: obtaining an index table; intercepting a query for sensor data in runtime; extracting a characteristic parameter from a query condition; locating a block identifier of matching sensor data storage blocks in the index table by using the characteristic parameter; and loading the storage blocks into a memory space of a working processor; where the index table contains mapping relationships between block identifiers of sensor data storage blocks and characteristic attributes of sensor data.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Abstract: Disclosed herein are techniques for implementing a machine intelligence computer system that can proactively monitor user audiovisual feedbacks as ques for improving the machine learning and predictive data analytical processes. Based on the real-time feedbacks, the introduced proactive machine intelligence system (PMIS) can dynamically revise (e.g., by assigning different weights) and/or filter the gathered input data for machine learning purposes. The PMIS can also dynamically adjust the machine learning algorithms adapted in the predictive models based on user real-time feedbacks.

Abstract: A system and method that includes receiving a layout of an integrated circuit (IC) device. A template library is provided having a plurality of parameterized shape elements. A curvilinear feature of layout is classified by selecting at least one of the parameterized shape elements that defines the curvilinear feature. A template index is associated with the layout is formed that includes the selected parameterized shape element. The template index and the layout can be delivered to a mask writer, which uses the template index and the layout to fabricate a pattern on a photomask.

Abstract: An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.

Abstract: A system comprises an electron beam directed toward a three-dimensional object with one tilting angle and at least two azimuth angles, a detector configured to receive a plurality of scanning electron microscope (SEM) images from the three-dimensional object and a processor configured to calculate a height and a sidewall edge of the three-dimensional object.

Abstract: A pixel array, a pixel structure, and a driving method of a pixel structure are provided. The pixel structure includes a first scan line, a second scan line, a first common electrode line, a data line, a first active device, a second device, a first pixel electrode, and a second pixel electrode. The data line is intersected with the first scan line and the second scan line. The first active device is driven by the first scan line and connected to the data line. The second active device is driven by the second scan line and connected to the first common electrode line. The first pixel electrode is electrically connected to the data line through the first active device. The second pixel electrode is electrically connected to the data line through the first active device and electrically connected to the first common electrode line through the second active device.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.