Abstract: A method of establishing a process operational framework in accordance with a context concept is introduced. The method involves establishing a process operational framework in accordance with a context concept in a manner that the process operational framework thus established applies to the process-oriented streamlining of an enterprise information system, project execution, and the other working needs. The method is flexible and adaptive to different enterprise operation context in terms of working, reduces the time and financial resources spent on customizing systems for use by different customers, and enhances the ease of maintenance of the enterprise process management system.

Abstract: A method of checking joule heating of an integrated circuit design, the method includes dividing the integrated circuit design into a plurality of windows, determining a power index of each window, adjusting the specification current value associated with each of the corresponding windows, and generating a current violation report, by a processor, of the integrated circuit. Each window includes one or more circuit elements. Each circuit element is associated with a corresponding current value. Each window is associated with a corresponding specification current value. Each power index is associated with a corresponding window. An amount of adjustment of the specification current value is a function of the power index of each corresponding window. The current violation report includes one or more entries. Each entry is associated with at least a corresponding window and one or more corresponding current values which exceed the corresponding adjusted specification current value.

Abstract: A sealed bearing assembly comprises a bellows to allow a shaft swing and move, and maintains the sealing under stringent conditions.

Abstract: A pixel array includes a first color pixel unit, a second color pixel unit and a third pixel unit, and the first, second and third pixel units respectively include a scan line, a data line, an active device electrically connected to the scan line and the data line and a first pixel electrode electrically connected to the active device. The first pixel electrode has at least one first slit, and a first acute angle is formed between an extending direction of the first slit and an extending direction of the scan line. Any two of the first acute angle of the first color pixel unit, the first acute angle of the second color pixel unit, and the first acute angle of the third color pixel unit are different.

Abstract: Embodiments are provided for equalizing audio data for output by a speaker of an electronic device based on a local position or orientation of the electronic device. According to certain aspects, the electronic device can determine (858, 868) its local position based on various sensor data, and identify (870, 872) an appropriate equalization setting. In some cases, the electronic device can modify (876, 880) the equalization setting based on acoustic and/or optical data. The electronic device can apply (882) the modified or unmodified equalization setting to an audio signal and cause the speaker to output (886) the audio signal with the applied equalization setting.

Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

Abstract: A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.

Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.

Abstract: A ring-type fan includes a frame having a receiving space defined between an air inlet and an air outlet thereof and being provided along an inner side of the air outlet with an inward projected wall portion; an impeller assembly rotatably mounted in the receiving space and including spaced impellers outward extended from a hub, and a ring member connected to radially outer ends of the impellers and externally provided with a circle of stop section, which and the projected wall portion together define an air passage between them; and at least one pressure relief section defining an airflow guide on the frame to communicate with the receiving space and the air passage. Any backflow can be guided out of the frame via the air passage and the pressure relief section without interfering with the inflow of air, allowing the ring-type fan to have upgraded heat dissipation performance.

Abstract: A high-temperature superconducting film includes a SrTiO3 substrate, a single crystalline FeSe layer, and a protective layer with a layered crystal structure. The single crystalline FeSe layer is sandwiched between the SrTiO3 substrate and the protective layer via a layer-by-layer mode. An onset temperature of superconducting transition of the high-temperature superconducting film is greater than or equal to 54 K, and a critical current density of the high-temperature superconducting film is about 106 A/cm2 at 12 K.

Abstract: A method for making a high-temperature superconducting film includes loading a SrTiO3 substrate in an ultra-high vacuum system. A single crystalline FeSe layer is grown on a surface of the SrTiO3 substrate by molecular beam epitaxy. A protective layer with a layered crystal structure is grown by molecular beam epitaxy and covering the single crystalline FeSe layer.

Abstract: A method on a mobile device for providing an audio output to a user at a determined loudness level is described. A text input is received. A loudness level of an audio output, corresponding to the text input, is determined based on a volume setting of the mobile device and a non-linear adjustment of the volume setting. The audio output is provided to an audio output component at the determined loudness level.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.

Abstract: A computer program product is provided and includes a non-transitory tangible storage medium readable by a processing circuit and on which instructions are stored for execution by the processing circuit for performing a method. The method includes enabling retrieval of a keyboard pressed sequence of characters of a first type, permitting a re-selection of characters of a second type, which are associated with the keyboard pressed sequence of the characters of the first type and permitting modification of the keyboard pressed sequence of the characters of the first type to initiate a search for and retrieval of characters of the second type.

Abstract: An exemplary liquid crystal display (LCD) provides data lines, gate lines, and pixel units arranged as a matrix array. A method for driving the LCD includes a step of analyzing and determining polarities of one column of the pixel units as determining pixels, thereby defining a first polarity group and a second polarity group, and a step of sequentially applying corresponding data signals to a part of the whole pixel units that are arranged at same rows with the first polarity group in a part of a period of a frame. Corresponding data signals are sequentially applied to the other part of the whole pixel units that are arranged at same rows with the second polarity group in another part of a period of a frame.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

Abstract: A method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for said each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for a timing constraint violation during the STA of the IC design according to the lookup table and re-optimizing the identified risky cell(s) is to reduce risk for the timing constraint violation of the IC design.

Abstract: A pixel array substrate and a display panel are provided. The pixel array substrate includes a substrate, scan line groups, data lines, and pixel structures. The scan line groups are disposed on the substrate. The data lines are intersected with the scan line groups. The pixel structures are connected to the scan line groups and the data lines. Each pixel structure includes an active device group, a first pixel electrode, a second pixel electrode, and a connection electrode. The first pixel electrode is located between the second pixel electrode and the nth scan line group. The connection electrode is located at a side of the first pixel electrode adjacent to one data line. The second pixel electrode is electrically connected to the active device group through the connection electrode. The connection electrode, the first pixel electrode, and the second pixel electrode are of the same layer.