Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.

Abstract: Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin height and a 2D FinFET model for the FinFET device are used to create a 3D FinFET model. The 3D FinFET model takes into account the fin height, which is evaluated to identify fin height variations amongst FinFET devices within the design layout. For example, a fin height variation is determined based upon a proximity pattern density, a fin pitch, a gate length, or other parameters/measurements. A voltage threshold variation is determined based upon the fin height variation. This allows the design layout to be modified to decrease the variation.

Abstract: A pixel structure including a first electrode layer, a second electrode layer and a liquid crystal layer is provided. The first electrode layer includes a plurality of first electrodes and a plurality of second electrodes, wherein the first electrodes are used for receiving a first driving voltage, and the second electrodes are used for receiving a second driving voltage. The second electrode layer includes a plurality of third electrodes and a plurality of fourth electrodes, wherein the third electrodes are used for receiving a third driving voltage and the fourth electrodes are used for receiving a fourth driving voltage. The liquid crystal layer is disposed between the first electrode layer and the second electrode layer. The first electrodes and the second electrodes are alternately disposed along a first direction parallel to the liquid crystal layer, and the third electrodes and the fourth electrodes are alternately disposed along the first direction.

Abstract: Embodiments are provided for equalizing audio data for output by a speaker of an electronic device based on a local position or orientation of the electronic device. According to certain aspects, the electronic device can determine (858, 868) its local position based on various sensor data, and identify (870, 872) an appropriate equalization setting. In some cases, the electronic device can modify (876, 880) the equalization setting based on acoustic and/or optical data. The electronic device can apply (882) the modified or unmodified equalization setting to an audio signal and cause the speaker to output (886) the audio signal with the applied equalization setting.

Abstract: A liquid crystal display panel includes a first substrate, a conductive line, an active switch device, a pixel electrode and a first electrode. The pixel electrode has a cruciform opening, which includes a first slit extending along a first direction and a second slit extending along a second direction intersecting the first slit. The first electrode is disposed on the first substrate and located adjacent to the periphery of the pixel electrode. The pixel electrode includes two first parts and a second part, where the two first parts are respectively disposed adjacent to two opposite ends of the second slit in the second direction. The distance between the two first parts in the second direction has a first width, the second part has a second width in the second direction, and the first width is greater than the second width.

Abstract: A method for accessing a flash memory includes: sending a write command and a set of corresponding data, wherein the data is for updating a part of contents of a first physical page, corresponding to a logical page, of a physical block in a flash memory; searching the physical block according to the write command for a second physical page that is allowed to be written; writing the data to the second physical page; and recording that the second physical page corresponds to the logical page.

Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

Abstract: A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.

Abstract: In some embodiments, in a method performed by at least one processor, a cell is characterized, by the at least one processor, with respect to an input transition characteristic considering different circuit topologies of a pre-driver driving the cell resulting in the same input transition characteristic.

Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.

Abstract: An electronic control apparatus including motion sensors is integrated in a portable electronic device to responsively control a media content stored in the portable electronic device, in response to motion sensor signals to flip, zoom, displace images/pages of the media content displayed on a display field of a display thereof. Accordingly, a responsive control method includes the steps of: presetting a first threshold angle; sensing an first rotation angle of the portable electronic device to send out a first rotation sensing signal as a rotation of a yaw, pitch or roll of a portable electronic device detected by a sensing module including motion sensors; and receiving the first rotation sensing signal to calculate and determine whether the first rotation angle is greater than the first threshold angle to responsively control a media content stored in an electronic control apparatus be flipped, zoomed or displaced when the first rotation angle is greater than the first threshold angle.

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

Abstract: An image fusion method and an image processing apparatus are provided. A first image is generated based on a first photographing parameter, and a second image is generated based on a second photographing parameter. A first pixel reference value of each of first pixels is calculated by using a self-define mask according to color components and a luminance component of the first pixels on the first image. A second pixel reference value of each of second pixels is calculated by using the self-define mask according to color components and a luminance component of the second pixels on the second image. A synthesizing reference map recording a plurality of synthesizing weights is obtained by comparing the first pixel reference value and the corresponding second pixel reference value. A fusion image is obtained by synthesizing the first image and the second image according to the synthesizing reference map.