Abstract: A fan with integrated vibration absorbing structure includes a fan frame, a hub-blade assembly, and at least one vibration absorber. The fan frame includes a base and at least one side wall formed around the base, and the hub-blade assembly is arranged in the fan frame. The at least one vibration absorber is provided on the at least one side wall to project therefrom for absorbing vibration produced by the fan during the operation thereof. Therefore, with the vibration absorbers integrated into the fan frame, it is no longer necessary to provide any additional vibration-absorbing member while upgraded vibration-absorbing effect can be achieved. Meanwhile, the fan can be more conveniently mounted at reduced mounting cost.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: An optical thin film includes: a transparent substrate including a first surface and a second surface which is opposite to the first surface; a first light-condensing layer formed on the first surface of the transparent substrate, the first light-condensing layer having a haze value ranging from 5% to 30% and a surface roughness ranging from 0.1 RMS to 1 RMS; and a second light-condensing layer formed on the second surface of the transparent substrate. The second light-condensing layer has a haze value ranging from 70% to 100% and a surface roughness ranging from 1 RMS to 10 RMS.

Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.

Abstract: A knife is provided. The knife comprises a handle and a blade configured to pivot with respect to the handle between an open position wherein a cutting edge of the blade is exposed and a closed position wherein the cutting edge of the blade is disposed within the handle, the blade including an abutting surface. The knife may further comprise a locking assembly configured to releasably lock the blade in the open position, the locking assembly comprising a biased, rotatable member having a canted surface for engaging a corresponding surface on the blade, wherein the canted surface and the corresponding surface are configured to secure the blade relative to the handle in the open position.

Abstract: A pixel structure including a first electrode layer, a second electrode layer and a liquid crystal layer is provided. The first electrode layer includes a plurality of first electrodes and a plurality of second electrodes, wherein the first electrodes are used for receiving a first driving voltage, and the second electrodes are used for receiving a second driving voltage. The second electrode layer includes a plurality of third electrodes and a plurality of fourth electrodes, wherein the third electrodes are used for receiving a third driving voltage and the fourth electrodes are used for receiving a fourth driving voltage. The liquid crystal layer is disposed between the first electrode layer and the second electrode layer. The first electrodes and the second electrodes are alternately disposed along a first direction parallel to the liquid crystal layer, and the third electrodes and the fourth electrodes are alternately disposed along the first direction.

Abstract: An integrated circuit and method for establishing scan test architecture in the integrated circuit is provided. The integrated circuit includes a plurality of circuit modules. Each circuit module includes a clock control unit, a first pipeline unit, a serialized compressed scan circuit and a second pipeline unit. The clock control unit generates a scan clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the scan clock. The serialized compressed scan circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scan clock. The scan clock of each of the circuit modules is independent from the scan clocks of the other circuit modules, thereby reducing the difficulty and cost of timing analysis and adjustment.

Abstract: A pixel structure including a first active device, a second active device, a first pixel electrode, a second pixel electrode, a third pixel electrode, a coupling electrode, and a capacitance electrode is provided. The first pixel electrode connected to the first active device and defines a first to a fourth liquid crystal alignment domain having different alignment directions. The second pixel electrode is connected to the coupling electrode and defines a fifth to an eighth liquid crystal alignment domain having different alignment directions. The third pixel electrode is connected to the second active device and defines a ninth and a tenth liquid crystal alignment domain. The coupling electrode is connected between the first active device and the second active device and extended to pass through the first, the second, and the third pixel electrodes. The capacitance electrode respectively overlaps parts of the first, the second, and the third pixel electrodes.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first regions and a plurality of second regions. The first regions and the second regions are formed on the first substrate and the second substrate. In a narrow viewing mode, the luminous flux of the first regions along a first viewing direction is different from that of the first regions along a second viewing direction opposite to the first viewing direction, and the luminous flux of the second regions along the first viewing direction is substantially different from that of the first regions along the first viewing direction.

Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Abstract: A liquid crystal display panel divided into a first and a second regions respectively having a plurality of sub-pixels arranged in array is provided. Each sub-pixel has a first display area providing a first main alignment vector, a second display area providing a second main alignment vector, and a compensation display area. A direction of the first main alignment vector is opposite to that of the second main alignment vector. When the liquid crystal display panel states in the narrow viewing angle display mode, driving voltages of the first display areas in the first region are substantially greater than driving voltages of the second display areas in the first region, driving voltages of the first display areas in the second region are smaller than driving voltages of the second display areas in the second region, and all the compensation display areas in the first and the second regions are enabled.

Abstract: A display panel includes a pair of substrates, a pixel structure, and a display medium layer disposed between the pair of substrates. The pixel structure is disposed on one of the substrates, and includes first and second sub-pixels. The first sub-pixel includes a first pixel electrode, wherein the first pixel electrode has a first spacing in a first main region and has a second spacing in a first minor region, wherein the second spacing is smaller than the first spacing. The second sub-pixel includes a second pixel electrode, wherein the second pixel electrode has a third spacing in a second main region and has a fourth spacing in a second minor region, wherein the fourth spacing is larger than or equal to the third spacing, and wherein the first spacing is larger than the third spacing.

Abstract: A fan serial connection structure includes a series fan assembly and a connection member assembly. The series fan assembly includes a first fan frame and a second fan frame serially connected with the first fan frame. The connection member assembly includes a first connection member and a second connection member. The first connection member has a first locating section and two first side sections respectively connected with two ends of the first locating section. The second connection member has a second locating section and two second side sections respectively connected with two ends of the second locating section. The first and second locating sections are respectively assembled and connected with two opposite sides of the series fan assembly in the serial connection position. The first and second side sections are respectively assembled and connected with two other opposite sides of the series fan assembly in the serial connection position.

Abstract: A serial fan assembling method includes the steps of providing a first and a second fan; providing a union member having a bottom panel and two side panels, which together define a receiving space having a top forming a first open side and two axially opposite ends respectively forming a second open side; connecting the first fan to the side panels of the union member via the first open side; and connecting the second fan to the side panels of the union member via the first open side, or connecting the second fan to the bottom panel of the union member via one of the second open sides, so that the first and the second fan connected to the union member are serially located in the receiving space and connected to each other.

Abstract: A fan serial connection structure includes a series fan assembly and a connection member. The series fan assembly includes a first fan and a second fan correspondingly serially connected with the first fan. The connection member is disposed on one side of the series fan assembly. The connection member has a first face and a second face opposite to the first face. The first face is correspondingly assembled with the side of the series fan assembly. According to the above structural design, the co-vibration of the series fan is offset or restrained to greatly reduce the vibration of the fan and lower the noise.

Abstract: A pixel array, a pixel structure, and a driving method of a pixel structure are provided. The pixel structure includes a first scan line, a second scan line, a first common electrode line, a data line, a first active device, a second device, a first pixel electrode, and a second pixel electrode. The data line is intersected with the first scan line and the second scan line. The first active device is driven by the first scan line and connected to the data line. The second active device is driven by the second scan line and connected to the first common electrode line. The first pixel electrode is electrically connected to the data line through the first active device. The second pixel electrode is electrically connected to the data line through the first active device and electrically connected to the first common electrode line through the second active device.

Abstract: A liquid crystal display panel divided into a first and a second regions respectively having a plurality of sub-pixels arranged in array is provided. Each sub-pixel has a first display area providing a first main alignment vector, a second display area providing a second main alignment vector, and a compensation display area. A direction of the first main alignment vector is opposite to that of the second main alignment vector. When the liquid crystal display panel states in the narrow viewing angle display mode, driving voltages of the first display areas in the first region are substantially greater than driving voltages of the second display areas in the first region, driving voltages of the first display areas in the second region are smaller than driving voltages of the second display areas in the second region, and all the compensation display areas in the first and the second regions are enabled.

Abstract: A mercaptoalkylsilatrane derivative having protecting group and a method of manufacturing the same. The mercaptoalkylsilatrane derivative includes: mercaptoalkylsilatrane compound having a mercapto group; a protecting group bonding to sulfur of the mercapto group, wherein the protecting group is used to avoid the chemical reaction of the mercapto group with reactive chemical species, e.g., oxygen, ketone, and aldehyde, etc. Besides, the manufacturing method thereof includes the steps of: providing silane compound having the mercapto group; bonding the protecting group to the mercapto group of the silane compound; performing the chemical reaction of triethanolamine with the silane compound having the protecting group for manufacturing the mercaptoalkylsilatrane derivative having the protecting group.

Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.