Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

Abstract: A light guide plate includes a light entry surface with first elongated elements, and a light exit surface with second elongated elements. Each of the first and second elongated elements serves to guide light, and has a cross-section in a shape of a circular segment.

Abstract: A display panel including a first substrate, a pixel array disposed on the first substrate, a first alignment layer covering the pixel array, a second substrate disposed opposite the first substrate, a second alignment layer disposed on the second substrate and a display medium disposed between the first alignment layer and the second alignment layer is provided. The first alignment layer has first alignment particles. A number of the first alignment particles each having an area ranged from 250 nm2 to 1000 nm2 occupies 40% or less of a total number of the first alignment particles in a unit area. The second alignment layer has second alignment particles. A number of the second alignment particles each having the area ranged from 250 nm2 to 1000 nm2 occupies 40% or less of a total number of the second particles in the unit area.

Abstract: An electronic system includes an electronic component, a heat dissipation device coupled on the electronic component and a retaining device around the electronic component. The heat dissipation device includes a base configured to contact the electronic component and a plurality of fins extending from the base. The base includes a coupling face forming a plurality of screw threads thereon. The retaining device includes at least a coupling face. The coupling face of the retaining device forms a plurality of screw threads for engaging with the screw threads of the coupling face of the base.

Abstract: A thin-film deposition apparatus comprises a chamber; a carrier in the chamber; a showerhead on the carrier, wherein the showerhead comprises multiple first gas-dispensing holes, multiple second gas-dispensing holes and multiple plasma-generating portions; and a first gas inlet system for providing a first process gas, wherein the first process gas outputted from the multiple first gas-dispensing holes.

Abstract: A Hydrocarbyl Carboxybetaine represented by Formula (1) is provided: wherein, n1?0 and n2>0, A is a C1-C20 alkyl group when n1>0, and A is a single bond when n1=0.

Abstract: An integrated circuit and method for establishing scan test architecture in the integrated circuit is provided. The integrated circuit includes a plurality of circuit modules. Each circuit module includes a clock control unit, a first pipeline unit, a serialized compressed scan circuit and a second pipeline unit. The clock control unit generates a scan clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the scan clock. The serialized compressed scan circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scan clock. The scan clock of each of the circuit modules is independent from the scan clocks of the other circuit modules, thereby reducing the difficulty and cost of timing analysis and adjustment.

Abstract: A liquid crystal display panel divided into a first and a second regions respectively having a plurality of sub-pixels arranged in array is provided. Each sub-pixel has a first display area providing a first main alignment vector, a second display area providing a second main alignment vector, and a compensation display area. A direction of the first main alignment vector is opposite to that of the second main alignment vector. When the liquid crystal display panel states in the narrow viewing angle display mode, driving voltages of the first display areas in the first region are substantially greater than driving voltages of the second display areas in the first region, driving voltages of the first display areas in the second region are smaller than driving voltages of the second display areas in the second region, and all the compensation display areas in the first and the second regions are enabled.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section, a first OTP section and a ROM section. The first MTP section includes a plurality of MTP cells, the first OTP section includes a plurality of OTP cells and the first ROM section includes a plurality of ROM cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section. The first ROM section is connected to a third word line, a third source line and the plurality of bit lines shared with the first MTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.

Abstract: The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: Embodiments are provided for equalizing audio data for output by a speaker of an electronic device based on a local position or orientation of the electronic device. According to certain aspects, the electronic device can determine (858, 868) its local position based on various sensor data, and identify (870, 872) an appropriate equalization setting. In some cases, the electronic device can modify (876, 880) the equalization setting based on acoustic and/or optical data. The electronic device can apply (882) the modified or unmodified equalization setting to an audio signal and cause the speaker to output (886) the audio signal with the applied equalization setting.

Abstract: A pixel structure includes a patterned insulating layer and a patterned electrode layer. The patterned insulating layer includes a first area and a second area, and the patterned electrode layer includes a third layer and a fourth layer. The first area has a plurality of bar-shaped structures, the third area is a block electrode, and the fourth area is composed of a plurality of first bar-shaped electrodes. The third area is disposed opposite to the first area such that the third area is protruded according to the bar-shaped structures thereby forming a plurality of second bar-shaped electrodes. The fourth area is disposed opposite to the second area such that the first bar-shaped electrodes are formed on the second area.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length.

Abstract: A tri-state liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a first electrode, a second electrode, a third electrode and a fourth electrode. The first substrate and the second substrate are disposed oppositely. The liquid crystal layer disposed between the first substrate and the second substrate includes a plurality of polymer network liquid crystals. The first electrode is disposed between the first substrate and the liquid crystal layer, the second electrode is disposed between the second substrate and the liquid crystal layer, and the first and second electrodes include planar electrodes. The third and fourth electrodes are disposed between the first substrate and the liquid crystal layer, and the third and fourth electrodes include patterned electrodes. The tri-state liquid crystal display panel has a transmission state display mode, a dark state display mode and a haze state display mode.

Abstract: A pixel structure includes a first conductive layer, a stacked layer, and a third conductive layer. The first conductive layer includes a first gate, a first scan line connected to the first gate, and a capacitor electrode separated from the first scan line. The stacked layer includes a semiconductor layer and a second conductive layer. The second conductive layer includes a data line, a first source connected to the data line, a second source, a first drain, a second drain, a connecting electrode connected to the second source and electrically connected to the first drain, and a coupling electrode connected to the second drain. The third conductive layer includes a first pixel electrode connected to the first drain, a second pixel electrode electrically connected to the connecting electrode, a first extending portion, and a second extending portion.

Abstract: An interface test device includes several interfaces, a test signal input interface, a control signal input interface, and a control module. The interface test device is connected between an electronic device and a computer. The interface test device receives control signals from the computer through the control signal input interface. The interface test device selectively outputs test signals to the electronic device through test interfaces corresponding to the control signals.