Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.

Abstract: A method and apparatus for applying database partitioning in a multi-tenancy scenario is disclosed, the method includes providing, in each database table of a partitioned database system storing tenant data, a partition key field for storing a respective partition key for each tenant within a plurality of tenants. The respective partition key for each tenant is designated for each tenant according to a partition designated for the each respective tenant and the corresponding relationships between partitions and partition keys in the database partitioning mechanism of the partitioned database system. The respective partition key is used by the partitioned database system to perform database partitioning operations on the data of each respective tenant.

Abstract: A pixel structure electrically connected to a data line and a scan line, and including a first and a second active device, a first and a second pixel electrode, and a first and a second capacitance electrode is provided. The first pixel electrode electrically connected to the first active device includes a first and a second electrode block electrically connected to each other. The second pixel electrode electrically connected to the second active device is electrically insulated from the first pixel electrode and separates the first and the second electrode block. The first pixel electrode respectively forms a first and a second capacitor with the first and the second capacitance electrode. The second pixel electrode respectively forms a third and a fourth capacitor with the first and the second capacitance electrode. The first and the second capacitor have different capacitances. The third and the fourth capacitor have different capacitances.

Abstract: The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.

Abstract: An apparatus and method for managing the distribution and expansion of public keys held by a group or array of systems in white lists. The addition of a new system to the array entails a manual input to authorize the introduction of the new system to one trusted system in the array. After the introduction the new system is trusted by the one member and the white list of the one member is loaded into the white list of the new system. The new system then requests joining each of the other systems in the array. For each system in the array asked by the new system, the systems in the array ask if any other systems in the array already trust the new member. In response, a system of the array that trusts the new system responds by sending its white list (containing the public key of the new system) to the requesting system. Eventually the public key of the new system is in the white lists of all the systems in the array.

Abstract: A system and method for authorizing administrative operations in a computer is provided. The computer initiates the split knowledge protocol upon an attempt by an administrator to invoke the operations. The administrator identifies a predetermined number of entities designated to authorize the operation. The computer creates a bit sequence and splits the bit sequence into a number of segments equal to the predetermined number of entities. Each entity thereafter decrypts a respective element to essentially authorize invocation of the operations. In response, the computer processes the decrypted segments to re-create the bit sequence. As an added level of security, the computer coma) pares the re-created bit sequence with the originally created sequence and, if they match, performs the operations.

Abstract: A pixel structure including a substrate, a scan line, a data line, an active device, a capacitor electrode and a pixel electrode is described. The substrate has a pixel region. The active device is electrically connected to the scan line and the data line. The capacitor electrode is disposed on the substrate. The pixel electrode is disposed in the pixel region and electrically connected to the active device, wherein the pixel electrode includes a first extending part, a second extending part and branches. The first extending part is disposed above the capacitor electrode and electrically coupling with the capacitor electrode, wherein the capacitor electrode is not completely covered by the first extending part. The second extending part has an extending direction different from that of the first extending part. The branches extend from the first extending part and the second extending part to an edge of the pixel region.

Abstract: A pixel array substrate and a display panel are provided. The pixel array substrate includes a substrate, scan line groups, data lines, and pixel structures. The scan line groups are disposed on the substrate. The data lines are intersected with the scan line groups. The pixel structures are connected to the scan line groups and the data lines. Each pixel structure includes an active device group, a first pixel electrode, a second pixel electrode, and a connection electrode. The first pixel electrode is located between the second pixel electrode and the nth scan line group. The connection electrode is located at a side of the first pixel electrode adjacent to one data line. The second pixel electrode is electrically connected to the active device group through the connection electrode. The connection electrode, the first pixel electrode, and the second pixel electrode are of the same layer.

Abstract: A round axial fan with balancing structure includes a hub; a ring-shaped band located around an outer side of the hub to thereby define an annular flow passage between the hub and the ring-shaped band; a plurality of blades located in the annular flow passage; and a plurality of recesses circumferentially spaced on and along the ring-shaped band, each of the recesses internally defining a receiving space for at least one balancing element to fit therein. With these arrangements, it is able to achieve weight balance of the round axial fan for the latter to rotate in a balanced state and to avoid any vibration due to unbalanced rotation of the round axial fan.

Abstract: A light emitting device includes a substrate and a plurality of pixel rows. The pixel rows are arranged on the substrate. Each of the pixel rows includes a first sub-pixel row having a plurality of first sub-pixels, a second sub-pixel row having a plurality of second sub-pixels, and a third sub-pixel row having a plurality of third sub-pixels. In the mth pixel row, each first sub-pixel includes a first structure layer, the first structure layers are separated from each other and each corresponds to one first sub-pixel. In the (m+n)th pixel row, the first sub-pixels include a first common structure layer, the first common structure layer corresponds to a plurality of first sub-pixels in a same row. The first structure layer and the first common structure layer commonly act as an organic functional layer or an electrode layer, and m, n are each a positive integer.

Abstract: A light emitting device includes a substrate and a plurality of pixel rows. The pixel rows are arranged on the substrate. Each of the pixel rows includes a first sub-pixel row having a plurality of first sub-pixels, a second sub-pixel row having a plurality of second sub-pixels, and a third sub-pixel row having a plurality of third sub-pixels. In the mth pixel row, each first sub-pixel includes a first structure layer, the first structure layers are separated from each other and each corresponds to one first sub-pixel. In the (m+n)th pixel row, the first sub-pixels include a first common structure layer, the first common structure layer corresponds to a plurality of first sub-pixels in a same row. The first structure layer and the first common structure layer commonly act as an organic functional layer or an electrode layer, and m, n are each a positive integer.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first regions and a plurality of second regions. The first regions and the second regions are formed on the first substrate and the second substrate. In a narrow viewing mode, the luminous flux of the first regions along a first viewing direction is different from that of the first regions along a second viewing direction opposite to the first viewing direction, and the luminous flux of the second regions along the first viewing direction is substantially different from that of the first regions along the first viewing direction.

Abstract: Class D amplifier is provided. The class D amplifier includes at least a block; each block includes an input circuit, an integrator, a comparator, a driving circuit and two feedback circuits. The input circuit receives a digital input to provide a differential pair of a positive and a negative input signals. The integrator receives the positive and negative input signals and a pair of positive and negative feedback signals for providing a positive error signal according to the positive input signal and the negative feedback signal, and providing a negative error signal according to the negative input signal and the positive feedback signal. The comparator compares between the positive and the negative error signals such that the driving circuit generates a driving output signal according to comparison result. The two feedback circuits respectively providing said positive and negative feedback signals according to the driving output signal.

Abstract: Methods for generating a device layout are provided. First, design rules corresponding to a specific technology are received. A selection of at least one element and a parameter value corresponding to at least one parameter on the selected element are received. A draft device layout corresponding to the selected element is generated by a device generator by referencing the parameter value and the design rules. A script is then executed to modify the draft device layout to generate an updated device layout. The script includes at least one command, and when the script is executed, the at least one command is performed to modify the parameter value of the at least one parameter of the selected element and cause the device generator to delete the old draft device layout and generate a new draft device layout by referencing the modified parameter value and the design rules.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.

Abstract: A system and method provides for secure initialization and booting of a security appliance. The security appliance cooperates with a “smart” system card to provide cryptographic information needed to boot the security appliance in accordance with a secure boot procedure. The initialization procedure commences once the security appliance detects the presence of the smart card. The smart card and an encryption processor perform an authentication and key exchange procedure to establish a secure communication channel between them. The system card then loads a twice wrapped master key from a configuration database and decrypts the master key using a key associated with the system card. The wrapped master key is then forwarded via the secure communication channel to the encryption processor, which decrypts the wrapped key using a key associated therewith and enters an operating state using the decrypted master key.

Abstract: A method, system and computer program for processing materialized tables in a multi-tenant application system, wherein in the multi-tenant application system, a plurality of tenants share one or more basic-tables. According to the data access history information of the plurality of tenants, an update pattern analyzer analyzes the similarity of the update patterns for one or more basic-tables by the plurality of tenants. Furthermore, according to the similarity analyzed by the update pattern analyzer, a tenant grouping means groups the plurality of tenants into a plurality of tenant groups. Additionally, according to the tenant groups grouped by the tenant grouping means, a materialized table constructor constructs the tenant group materialized tables from the one or more basic-tables.

Abstract: Strings entered into a computer system are converted to a common language. The process of converting strings to a common language comprises determining a user-selected target language, associating a user-selected primary input language with the target language and associating a user-selected secondary input language with the target language. The process further comprises obtaining a string of at least one character, converting the obtained string from the primary input language to the target language if the obtained string corresponds to a valid string in the primary input language and converting the obtained string from the secondary input language to the target language if the obtained string corresponds to a valid string in the secondary input language and is not a valid string in the primary input language.

Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.