Abstract: An image privacy protecting method is provided. Positions of a privacy protecting region and a normal display region are acknowledged first. When a frame of image is processed, a first image data will be displayed in the privacy protecting region is processed in a narrow viewing mode to obtain a narrow viewing driving data, and a second image data will be displayed in the normal display region is processed in a wide viewing mode to obtain a wide viewing driving data. Finally, display operations are performed in the privacy protecting region and the normal display region respectively according to the narrow viewing driving data and the wide viewing driving data.

Abstract: An LCD panel with color washout improvement. In one embodiment, the LCD panel includes a plurality of pixels spatially arranged in a matrix form, each pixel defined between a respective pair of scanning lines (Gn, Gn—CS) and two neighboring data lines Dm and Dm+1, comprising a pixel electrode, a first transistor electrically coupled to the scanning lines Gn, the date line Dm and the pixel electrode, and a second transistor electrically coupled to the scanning lines Gn—CS and the pixel electrode such that when N pairs of scanning signals to the N pairs of scanning lines {Gn, Gn—CS} and a plurality of data signals to the data lines, the pixel electrode of each pixel has a first voltage at the first duration of a frame period, and a second voltage at the second duration of the frame period, respectively. The first and second voltages are substantially different from each other.

Abstract: A computer-implemented method for virally updating software in a networked computer including performing neighbor computer discovery using the networked computer to ascertain neighbor computers and ascertaining, using the networked computer, whether any of the neighbor computers possesses an update package configured for updating the software. If a neighbor computer of the neighbor computers possesses the update package, the method includes retrieving the update package to the networked computer and updating the software in the networked computer using the update package.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A memory managing method for an electronic system is provided. The electronic system includes an auxiliary memory, and is capable of communicating with a flash memory including a plurality of blocks. Each of the blocks has a logical/physical address mapping relationship. The address mapping relationships are stored in a storage region in the flash memory. The memory managing method first determines whether the address mapping relationships stored in the storage region are correct. The address mapping relationships are copied from the storage region to the auxiliary memory when a determination result is affirmative.

Abstract: A shoe apparatus includes a shoe, a power supply and a wireless transmitter. The shoe is to be worn by a user. The power supply is provided in the shoe for generation and storage of electricity. The power supply includes a battery, a first generator unit electrically connected to the battery and a second generator unit electrically connected to the battery. The wireless transmitter is provided in the shoe and electrically connected to the power supply for wireless communication of data with a remote device.

Abstract: A photovoltaic device includes: a back electrode; a transparent front electrode; a p-type semiconductor layer disposed between the transparent front electrode and the back electrode and made from a first semiconductor compound including M1, M2, and A1, the p-type semiconductor layer having a M1/M2 atomic ratio; and an n-type layered structure disposed between the p-type semiconductor layer and the transparent front electrode and cooperating with the p-type semiconductor layer to form a p-n junction therebetween. The n-type layered structure includes an n-type semiconductor layer made from a second semiconductor compound including M3, M4, and A2 and having a M3/M4 atomic ratio less than the M1/M2 atomic ratio and greater than 0.1 and less than 0.9.

Abstract: A system and method efficiently deletes a file from secure storage, i.e., a cryptainer, served by a storage system. The cryptainer is configured to store a plurality of files, each of which stores an associated file key within a special metadata portion of the file. Notably, special metadata is created by a security appliance coupled to the storage system and attached to each file to thereby create two portions of the file: the special metadata portion and the main, “file data” portion. The security appliance then stores the file key within the specially-created metadata portion of the file. A cryptainer key is associated with the cryptainer. Each file key is used to encrypt the file data portion within its associated file and the cryptainer key is used to encrypt the part of the special metadata portion of each file. To delete the file from the cryptainer, the file key of the file is deleted and the special metadata portions of all other files stored in the cryptainer are re-keyed using a new cryptainer key.

Abstract: The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout.

Abstract: A computer implemented method for locating isolation points in an application under multi-tenant environment includes scanning, using a computer device an application by using scanning rules, to obtain potential isolation points and relationships between the potential isolation points; specifying at least one isolation point among the potential isolation points; and screening an isolation point from the potential isolation points by using relationships between the specified at least one isolation point and the remaining potential isolation points.

Abstract: An apparatus for locating isolation points in an application under multi-tenant environment includes a scanning module configured to scan the application, by using scanning rules, to obtain potential isolation points and relationships between the potential isolation points; a specifying module configured to specify at least one isolation point among the potential isolation points; and an isolation point screening module configured to screen an isolation point from the potential isolation points by using relationships between the specified at least one isolation point and the remaining potential isolation points.

Abstract: A protection component includes: a package substrate; a first fuse unit disposed in the package substrate, having a first fusing region; a second fuse unit disposed in the package substrate, having a second fusing region which is close to the first fusing region; and a first buried cave disposed in the package substrate corresponding to the first and second fusing regions. When one of the first and second fusing regions is blown out, the first buried cave assists energy of fuse melting to break the other of the first and second fusing regions.

Abstract: A sub-pixel circuit, display panel and driving method of the display panel are provided. The display panel has a plurality of data lines, scan lines and sub-pixel circuits. At least one of the sub-pixel circuits is electrically coupled to one data line and three scan lines. The sub-pixel circuit determines whether to receive data from the coupled data line or not according to scan signals transmitted on the coupled three scan lines, and controls transmittance itself accordingly. Specifically, the scan signals transmitted on the coupled three scan lines are different from each other.

Abstract: A three-dimensional (3D) display including a display panel and a phase retardation film is provided. The display panel has a plurality of first pixel regions and a plurality of second pixel regions that are arranged as an array. The phase retardation film is disposed on the surface of the display panel. The phase retardation film has a plurality of first retardation regions and a plurality of second retardation regions that are alternately arranged. The first retardation regions have the same phase retardation, the second retardation regions have the same phase retardation, and the phase retardation of the first retardation regions is different from that of the second retardation regions. All the regions of the phase retardation film have the same transmittance. A display method adaptable to the 3D display is also provided.

Abstract: An exemplary display apparatus includes a plurality of pixel units, a plurality of gate lines, a readout line and a plurality of touch control units. The gate lines are for deciding whether to enable the pixel units. Each of the touch control units is electrically coupled to the readout line and a corresponding one of the gate lines and includes a switching element. When one of the touch control units is touched, the switching element of the touched touch control unit is turned on, and thereby a waveform on the gate line corresponding to the touched touch control unit is coupled to the readout line and a position of the touched touch control unit is determined according to a timing sequence of a waveform on the readout line. The present invention also provides a touch detection method adapted to be implemented on the above-mentioned display apparatus.

Abstract: A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.

Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract: A symmetrical series fan structure includes multiple frame bodies made with single mold. Each frame body has a first through hole, a second through hole and a base having multiple connection members. The base is positioned in the second through hole on one side of the frame body and connected to the frame body via the connection members. The frame body has multiple fixing members and multiple fixing holes on the same side of the frame body as the base. The frame bodies are serially connected by means of inserting the fixing members into the fixing holes with the bases and the connection members of the frame bodies attached to each other. Accordingly, the frame bodies can be made with single mold and assembled to form the symmetrical series fan structure. In this case, the mold development cost is saved and the manufacturing cost is lowered.

Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.