Abstract: A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

Abstract: A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, the thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant.

Abstract: A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads.

Abstract: A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop.

Abstract: Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided. When the non-planar printing stencil is pressed against the chip carrier, the non-planar printing stencil is compliantly in contact with the substrate core and the stiffener and a plurality of printing openings of the non-planar printing stencil exposes the substrate core within the die-attaching units. During stencil printing, die-attach material fills in the printing openings to directly adhere to the substrate core. Therefore, the warpage of the substrate core is restrained to avoid bleeding of die-attach material so that die-attach materials can be formed as a die-attach layer with a uniform thickness on core-exposed chip carrier with lower costs.

Abstract: A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections.

Abstract: A substrate strip for semiconductor packages to slow the crack growth, primarily comprises a molding area and two side rails. The molding area includes a plurality of packaging units. The side rails are located outside the molding area and include two opposing longer sides of the substrate strip. A metal mesh is disposed on the side rails. The metal mesh consists of a plurality of crisscrossed wires having a plurality of isolated wire terminals at one edge of the metal mesh. Accordingly, crack growth is slowed by the specific metal mesh without damaging the packaging units. In one embodiment, the metal mesh is without boundary wires connecting to the isolated wire terminals to enhance the resistance to crack growth.

Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.

Abstract: A non-planar substrate strip for semiconductor packages is revealed, primarily comprising a substrate core having an external surface, an external solder mask and a patterned thick solder mask. The external solder mask covers the external surfaces of a plurality of substrate units of the non-planar substrate strip. The patterned thick solder mask is formed on the opposing surface of the substrate core only to cover a frame of the substrate core to expose the die-attaching surface of the substrate units. The patterned thick solder mask is thicker than the external solder mask. Therefore, the substrate strengths and die-attaching strengths of the substrate strip are enhanced. The substrate warpage is restrained during manufacturing the substrate strip. A semiconductor packaging method utilizing the substrate strip is also revealed.

Abstract: A substrate with reduced substrate warpage and a semiconductor package utilizing the substrate are revealed. The substrate primarily comprises a core where a wiring layer and a first solder mask are formed on one surface of the core, and a second solder mask and a die-attaching layer are formed on the other surface of the core. The first solder mask has a thickness difference with respect to the second solder mask in a manner to reduce the warpage of the substrate caused by thermal stresses due to temperature differences can be well under control. Therefore, the manufacturing cost of the substrate can be lower without adding extra stiffeners to achieve substrate warpage control during semiconductor packaging processes.

Abstract: A substrate panel is revealed, comprising a plurality of substrate strips where each substrate strip has a plurality of substrate units and a plurality of appropriative ID marks. Each ID mark is corresponding to and formed on each substrate unit. All of the ID marks are different in a manner to simultaneously recognize both the relative locations of the substrate units to the substrate strips and the relative locations of the substrate strips to the substrate panel. In a preferred embodiment, the ID marks are disposed on exposed surfaces of the substrate units so that it is still visible after semiconductor packaging. Therefore, during or after semiconductor packaging processes, any defect found can be traced back by the ID marks on the substrate units to recognize the locations of the substrate units in the substrate panel for failure analysis to improve PCB manufacturing processes or semiconductor packaging processes for better production yields.

Abstract: Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.

Abstract: A pillar-to-pillar flip-chip assembly primarily comprises a substrate, a chip disposed on the substrate, a plurality of first copper pillars on the bonding pads of the chip, a plurality of second copper pillars on the bump pads of the substrate, and a soldering material. A first height of the first copper pillars protruding from the active surface of the chip is the same as a second height of the second copper pillars from the solder mask on the substrate. When the soldering material electrically and mechanically connects the first copper pillars to the second copper pillars, a plurality of central points of the soldering material are formed on an equal-dividing plane between the chip and the substrate to reduce the direct stresses exerted at the soldering material to avoid peeling or breaks from the bump pads. Moreover, each of conventional solder balls is replaced with two soldered copper pillars to meet the lead-free requirements with higher reliability and lower costs.

Abstract: A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.

Abstract: A circuit substrate ready to slot is revealed, primarily comprising a board base with slot-reserved area. A plurality of bonding fingers, a plating bus loop, and a plurality of plating lines disposed on the bottom surface of the board base. The bonding fingers are located adjacent to but outside the slot-reserved area and the plating bus loop is located inside the slot-reserved area. The plating lines connect the bonding fingers to the plating bus lines. The plating bus loop includes two side bars closer to the long sides of the slot-reserved area than the bonding fingers to the long sides. Accordingly, the lengths of the plating lines within the slot-reserved area are shortened. It is possible to solve the issues of metal burs and shifting of the remaining plating lines when routing a slot along the peripheries of the slot-reserved area. Moreover, the plating current can evenly distribute to improve the plating qualities on the surfaces of the bonding fingers.

Abstract: Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided. When the non-planar printing stencil is pressed against the chip carrier, the non-planar printing stencil is compliantly in contact with the substrate core and the stiffener and a plurality of printing openings of the non-planar printing stencil exposes the substrate core within the die-attaching units. During stencil printing, die-attach material fills in the printing openings to directly adhere to the substrate core. Therefore, the warpage of the substrate core is restrained to avoid bleeding of die-attach material so that die-attach materials can be formed as a die-attach layer with a uniform thickness on core-exposed chip carrier with lower costs.

Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.

Abstract: A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate.

Abstract: A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.