Abstract: A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.

Abstract: A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.

Abstract: A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.

Abstract: A semiconductor device having package-on-package (POP) configuration, primarily comprises a plurality of vertically stacked semiconductor packages and a plurality of electrical connecting components such as solder paste to electrically connect the external terminals of the semiconductor packages such as external leads of leadframes. Each semiconductor package has an encapsulant to encapsulate at least a chip where the encapsulant is movable with respect to the electrical connecting components to absorb the stresses between the vertically stacked semiconductor packages. In one embodiment, a stress-releasing layer is interposed between the vertically stacked semiconductor packages.

Abstract: A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip.

Abstract: A semiconductor package with crack-restraining ring surfaces is revealed, primarily comprising a chip carrier, a chip disposed on the chip carrier, and a plurality of belfry-like bumps. The belfry-like bumps are disposed on a plurality of corresponding conductive pads on the bottom surface of the chip carrier as external terminals. Each belfry-like bump has at least a crack-restraining ring surface parallel to the conductive pads and between the top of the belfry-like bump and the conductive pad to prevent the spreading of the soldering cracks and to enhance the soldering strengths at the micro contacts to achieve higher package reliability.

Abstract: A stackable semiconductor package is revealed, primarily comprising a chip carrier, a chip, and a plurality of bottom bump sets. The chip carrier has a plurality of stacking pads disposed on the top surface and a plurality of bump pads on the bottom surface. The chip is disposed on and electrically connected to the chip carrier. The bottom bump sets are disposed on the corresponding bump pads and each consists of a plurality of conductive pillars. Solder-filling gaps are formed between the adjacent conductive pillars for filling and holding solder paste so that the soldering area can be increase and the anchoring effect can be enhanced due to complicated the soldering interfaces to achieve higher soldering reliability and less cracks at the soldering interfaces.

Abstract: A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

Abstract: A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of the semiconductor package, the external terminals are divided into at least two different groups. In one of the embodiment, different groups of the external terminals are bumps with non-equal heights to achieve a uniform standoff plane to compensate the warpage of the substrate. The predicted substrate warpage can be compensated without causing any soldering defects. In another embodiment, a plurality of compensating bumps are selectively disposed on one group of the external terminals with larger stacking gaps.

Abstract: A memory module capable of lessening shock stresses, primarily comprises a multi-layer printed circuit board (PCB), a plurality of memory packages, and a stress-buffering layer. The memory packages are disposed at least on one of the rectangular surfaces of the PCB. The stress-buffering layer is disposed at least on both short sides of the PCB and extended to the two rectangular surfaces to reduce the impact stresses. Preferably, the stress-buffering layer is further disposed on the other long side of the PCB opposite to the one with disposed gold fingers.

Abstract: A substrate improving immobilization of ball pads for BGA packages mainly comprises a substrate core, a plurality of ball pads and a solder resist layer. Each of the ball pads has a metal pad and at least a metal nail. The metal pads are adhered on a surface of the substrate core and the metal nails are embedded into but not penetrate the substrate core. The solder resist layer is formed over the substrate core and exposes the metal pads. By utilizing the shapes of the ball pads to increase bonding area between the ball pads and the substrate core, a separation or crack occurring at the interface between the metal pads and the substrate core can be substantially avoided.

Abstract: A semiconductor package is revealed, primarily comprising a substrate, a chip disposed on the substrate, and an encapsulant to encapsulate the chip. The substrate has a plurality of dimples formed in its top surface thereof without penetrating through the substrate and located at a non-wiring region outside a chip mounting region. Therefore, without changing the appearance of the semiconductor package, the diffusion path of moisture and the adhesive strength between the encapsulant and the substrate can be increased to achieve functions of anti-humidity and anti-delamination.

Abstract: A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball.

Abstract: A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.

Abstract: A chip package and a lead frame used in the chip package are disclosed. The lead frame includes a plurality of first side leads and a plurality of second side leads where the first side leads have a plurality of first bent leads extending from a first edge and the second side leads have a plurality of second bent leads extending from a second edge. The inner ends of the first bent leads and the inner ends of the second bent leads are facing to a third edge between the first and second edges and are connected to the lead frame. Therefore, the lengths of the first side leads are equal and symmetrical to the ones of the second side leads without any suspended long leads for chip attachment. The chip package is most suitable for packaging chips with bonding pads on one single side.

Abstract: An anti-impact memory module mainly comprises a multi-layer PWB (Printed Wiring Board), a plurality of memory packages and a plurality of first anti-impact bars. The PWB has two longer sides and two shorter sides. A plurality of gold fingers are disposed along one of the longer sides. The first anti-impact bars are disposed on one surface of the PWB and adjacent to the two shorter sides, which are higher than the memory packages in height. Preferably, at least a second anti-impact bar is formed at another longer side far away from the gold fingers. The first anti-impact bars and/or the second anti-impact bar can be utilized to cushion impact force for preventing the memory module product from damaging while fallen accidentally.

Abstract: An IC package with a near-substrate-scale die-attaching layer includes a substrate, a near-substrate-scale die-attaching layer, a chip, a plurality of bonding wires, an encapsulant, and a plurality of solder balls. A plurality of ball pads are formed on the bottom surface of the substrate for solder ball placement. The near-substrate-scale die-attaching layer is formed on the top surface of the substrate covering most of the top surface above the ball pads without extending to the edges of the top surface. The active surface of the chip is attached to a first portion of the near-substrate-scale die-attaching layer and is electrically connected to the substrate by the bonding wires. The encapsulant is formed above the top surface of the substrate to cover a second portion of the near-substrate-scale die-attaching layer extending between the substrate and the encapsulant.

Abstract: A substrate improving immobilization of ball pads for BGA packages mainly comprises a substrate core, a plurality of ball pads and a solder resist layer. Each of the ball pads has a metal pad and at least a metal nail. The metal pads are adhered on a surface of the substrate core and the metal nails are embedded into but not penetrate the substrate core. The solder resist layer is formed over the substrate core and exposes the metal pads. By utilizing the shapes of the ball pads to increase bonding area between the ball pads and the substrate core, a separation or crack occurring at the interface between the metal pads and the substrate core can be substantially avoided.

Abstract: A memory module for improving impact resistance mainly comprises a multi-layer PWB (Printed Wiring Board) and a plurality of memory packages. The multi-layer PWB is rectangular and has two longer sides and two shorter sides, wherein a plurality of gold fingers are disposed along one of the longer sides, at least an arc notch and a plurality of first stress-absorbing slots are formed at the two shorter sides respectively. Preferably, plural second stress-absorbing slots are formed at another longer side far away from the gold fingers. The impact stress due to accidental drop may be absorbed by the first stress-absorbing slots or/and the second stress-absorbing slots to prevent the product from damaging.

Abstract: A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.