Abstract: An IC package keeping the attachment level of leads on chip during molding process, mainly comprises a plurality of leads of a Lead-On-Chip (LOC) leadframe, a chip adhered under the leads, a plurality of bonding wires electrically connecting the chip to the leads, a plurality of first supporting columns disposed above some of the leads, a plurality of second supporting columns disposed under the some of the leads and a molding compound. The molding compound encapsulates the chip, the bonding wires, inner portions of the leads and sides of the first and second supporting columns. Therein, the first and second supporting columns are longitudinally corresponding to each other and adjacent the chip. The thickness including one of the first supporting columns, a corresponding one of the second supporting columns and one of the leads disposed corresponding to the selected first supporting column and the selected second supporting column is approximately as same as that of the molding compound.

Abstract: A BGA package with encapsulation on substrate bottom comprises a chip, a substrate, a molding compound and a plurality of solder balls. The substrate has a SMT surface placing a plurality of ball pads. The molding compound encapsulates a solder resist layer on the SMT surface of the substrate and has a plurality of through holes exposing the ball pads respectively. The hole diameter of the through holes is greater than that of the openings of the solder resist layer on the substrate to allow the solder balls not to contact the molding compound. The solder balls are disposed in the through holes and are bonded to the exposed ball pads of the substrate thereby enhancing moisture resistance of BGA products and preventing the solder balls from falling because of contact stress of the molding compound.

Abstract: A MAP (Mold Array Process) for chip encapsulation is disclosed in this invention. First, a substrate strip having a plurality of units is provided. A plurality of chips are disposed on the substrate strip and then an encapsulant is formed made by transfer molding to continuously encapsulate the chips on a plurality of units. Therein, the substrate strip includes at least a first row of units in a one-dimensional array and at least a second row of units in a one-dimensional array and connected with the first row of units in parallel, and the cutting lines between the first row of units are not aligned with those between the second row of units so that the first and second rows of units are disposed in a non-two-dimensional array. Therefore, the mold flows on the cutting lines and on centers of the chips can be balanced merely by means of modifying arrangement of the units without adding obstructions or other extra components to solve conventional encapsulation bubbles generated at sides of the chips.

Abstract: A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality of through holes penetrating the substrate at the edge of chip bearing area; an encapsulant used to cover those chip and filling those through holes to form a strengthened bump surrounding the chip bearing area on the lower surface of the substrate; and a plurality of conductive balls are respectively arranged on those electrical-connecting points. The present invention utilizes the strengthened bump on the bottom of the substrate to enhance the structure strength of the substrate so as to avoid the warpage of the substrate caused from the stress due to the temperature variation during the package process to affect the following processes.

Abstract: An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.

Abstract: A MAP (Mold-Array-Process) type semiconductor package mainly includes a chip carrier, at least a chip, and an encapsulant. The chip is disposed on the carrier and is electrically connected to the chip carrier. The encapsulant completely covers the upper surface of the chip carrier and encapsulates the chip. Therein, the encapsulant has two mold-flow constraining portions adjacent two opposite sides of the encapsulant, which are lower than the central top surface of the encapsulant and vertically aligned to the corresponding sawed sides of the chip carrier. Therefore, by changing the shape of the encapsulant, the mold flows on the chip and at the sides of the chip carrier will be the balanced to solve encapsulated bubble(s) formed on the rear side of the chip during MAP packaging, and disposition of conventional barrier components will be eliminated.

Abstract: An IC package structure of die face up or die face down is provided with adding the occupied area of die-attaching material. The die-attaching layer is distributed the surface of the substrate exposed by a die and configured for absorbing the thermal stress induced from thermal expansion mismatch of materials generated during a board level temperature cycle test.

Abstract: A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can resist the deformation and reduce the damage from the warpage and simultaneously enhance the yield and stability of the package structure.

Abstract: A PCB for mounting IC package is designed with dummy solder pads. Dummy solder pastes will spread on the dummy solder pads after screen printing process of solder paste. A substrate for a package of IC is designed with or without dummy solder pads. After mounting the package of IC onto the PCB, the dummy solder paste may or may not solder to the substrate of the package of IC. When the package of IC suffers external force, the dummy solder pastes can help provide supporting for the package of IC and increase the mechanical strength to avoid package or IC crack.

Abstract: A ball grid array structure includes a substrate, wherein a plurality of electric contacts are arranged on its lower surface; a chip arranged on the upper surface of the substrate and electrically connecting with those electric-connecting points; at least a through hole on the substrate and arranged around the edge of the chip; a molding compound covering the chip and filling the through hole to form a window-type bump on the lower surface of the substrate; and a plurality of conductive balls arranged on those electric-connecting points on the substrate. The present invention utilizes the window-type bump to enhance the structure strength of the substrate to effectively decrease the warpage of package in the curing process and to provide a support to prevent the crack of the package from the external force.