Abstract: A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder.

Abstract: This invention relates to a film comprising a heterogeneous blend of: 1) from 60 to 99 wt % of one or more semi-crystalline polymers; and 2) from 1 to 40 wt % of one or more semi-amorphous polymers; where the bend has: an MFR of 0.5 to 100 dg/min, a haze of 20% or less, and a permanent set of greater than 65%; and where the film is 2.5 to 635 microns thick and has: a haze of 10% or less, a 1° Secant tensile modulus of 100,000 to 30,000 psi, an Elmendorf tear in the machine direction and transverse direction of 45 g/mil or more, a total energy impact of 3 J or more; and a 45 degree gloss of 82 or more.

Abstract: A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associated with the first operand and the second operand is received. The operation is an addition or a subtraction. Three concurrent calculations are performed on the first operand and the second operand. The first concurrent calculation includes applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent. The applying the operation based on the first assumption results in a first result and includes utilizing a two cycle adder.

Abstract: A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.

Abstract: A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least one leading zero digit and set to one otherwise. The method also includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least two leading zero digits. A group two switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least two leading zero digits and set to one otherwise. The method further includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains three leading zero digits.

Abstract: A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.

Abstract: A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle.

Abstract: A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum.

Abstract: This invention relates to a molded article comprising a heterogeneous blend comprising: 1) from 60 to 99 weight percent of one or more semi-crystalline polymers (based upon the weight of the semi-crystalline and semi-amorphous polymers), each semi-crystalline polymer comprising propylene and from 0 to 5 weight % alpha-olefin comonomer (based upon the weight of the polymer), said semi-crystalline polymers each having a melting point between 100 and 170° C. and a melt flow rate of 200 dg/min or less; and 2) from 1 to 40 weight % of one or more semi-amorphous polymers (based upon the weight of the semi-crystalline and semi-amorphous polymers), each semi-amorphous polymer comprising propylene and from 10 to 25 weight % of one or more C2 and/or C4 to C10 alpha-olefin comonomers, said semi-amorphous polymers each having: a) a heat of fusion of 4 to 70 J/g; and b) a melt flow rate of 0.

Abstract: The present invention relates to a composition comprising more than 25 weight % (based on the weight of the composition) of one or more ethylene polymers having an Mw of 20,000 g/mole or more and at least 0.1 weight % of a liquid hydrocarbon modifier where the modifier has: 1) a viscosity index of 120 or more, and 2) an kinematic viscosity of 3 to 3000 cSt at 100° C., and 3) a pour point of ?10° C. or less, and 4) a flash point of 200° C. or more; and wherein the modifier contains less than 5 weight % of functional groups selected from hydroxide, aryls, substituted aryls, halogens, alkoxys, carboxylates, esters, acrylates, oxygen, nitrogen, and carboxyl, based upon the weight of the modifier.

Abstract: This invention relates to a nonwoven article comprising a heterogeneous blend comprising: 1) from 60 to 99 weight percent of one or more semi-crystalline polymers (based upon the weight of the semi-crystalline and semi-amorphous polymers), each semi-crystalline polymer comprising propylene and from 0 to 5 weight % alpha-olefin comonomer (based upon the weight of the polymer), said semi-crystalline polymers each having a melting point between 100 and 170° C. and a melt flow rate of 2000 dg/min or less; and 2) from 1 to 40 weight % of one or more semi-amorphous polymers (based upon the weight of the semi-crystalline and semi-amorphous polymers), each semi-amorphous polymer comprising propylene and from 10 to 25 weight % of one or more C2 and or C4 to C10 alpha-olefin comonomers, said semi-amorphous polymers each having: a) heat of fusion of 4 to 70 J/g; b) a Melt Flow Rate of 0.

Abstract: The invention relates to proton-conducting polymers, including tetrazole-containing polymers. Proton-conducting membranes useful for fuel cell applications are formed from mixtures of a polymer with one or more non-aqueous proton sources. In representative examples of the present invention, tetrazole groups are attached to a polymer backbone such as polyphosphazene, the tetrazole groups interacting with the proton source.

Abstract: An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O) buffer can be enabled and disabled in response to an ODT control signal. Additionally, the ODTs for a first set of the buffer circuits can be enabled and disabled responsive to the ODT control signal and the ODT for at least one of a second set of the buffer circuits is disabled.

Abstract: The present invention relates to the field of target tracking and more generally to a method employing improved algorithms, which achieve excellent tracking performance for a high-g maneuvering target. The two-model Interacting Multiple Model algorithm and the Interacting Acceleration Compensation algorithm will be modified by introducing adaptive factors through the detection of the normalized innovation squared which is chi-square probability distributed. The implementation results show that the modified algorithms can handle the target sudden maneuver better and are more accurate than the original algorithms.

Abstract: A process for making an ion-conducting polymer comprises cross-linking polymers having functional groups such as alkyne groups and azide groups. An example ion-conducting polymer has cross-links including nitrogen-containing heterocycles formed by the reaction between the functional groups, such as 1,2,3-triazole groups formed by a cycloaddition reaction between alkyne and azide groups. The ion-conducting polymer may be used in an ion-electrolyte membrane. Examples include a proton-electrolyte membrane useful for fuel cells.

Abstract: An example battery according to an embodiment of the present invention includes a positive electrode, a negative electrode, and an electrolyte. The positive electrode comprises a positive active material, and has a positive electrode area and a positive electrode capacity. The negative electrode comprises a negative active material, and has a negative electrode area and a negative electrode capacity. The battery has an electrode area ratio equal to the positive electrode area divided by the negative electrode area, and an electrode capacity ratio equal to the positive electrode capacity divided by the negative electrode capacity. In an example battery, the electrode area ratio is at least approximately one, and/or the electrode capacity ratio is at least approximately one.

Abstract: The present invention relates to a composition comprising 1) from 1 to 98 weight % of a first propylene polymer having a melting point of 100° C. or more, 2) from 5 to 98 weight % of a second propylene polymer having a heat of fusion of 70 J/g or less and a tacticity index of 75% or more, 3) from 0.

Abstract: This invention relates to the design and fabrication of micro electromechanical systems (MEMS) for applications in such varied fields as the biomedical, micro-fluidics and chemical analysis fields.

Abstract: The invention relates to an indicator comprising a light-guiding layer, a cladding layer on one surface of said light-guiding layer, and a patterning layer on the other surface.

Abstract: Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.