Patents by Inventor Wen Liao

Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220251325
    Abstract: A method for processing a polyalkylene benzenedicarboxylate material includes subjecting a polyalkylene benzenedicarboxylate material to an immersion treatment with an immersion liquid including ethylene glycol, so as to obtain an immersed polyester material, and subjecting the immersed polyester material to a disintegration treatment to obtain a disintegrated polyester material. The immersed polyester material has crystallinity higher than that of the polyalkylene benzenedicarboxylate material.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 11, 2022
    Applicant: National Taiwan University
    Inventors: Chia-Wen Wu, Wei-Sheng Liao, Yu-Wen Chiao
  • Publication number: 20220247131
    Abstract: An electrical connector includes at least one electrical module. The electrical module includes: an insulating body, where multiple first accommodating slots are concavely provided on a first side toward a second side of the insulating body; multiple first terminal assemblies, respectively accommodated in the corresponding first accommodating slots; and a first grounding member, having multiple first spokes and multiple second spokes. Each first terminal assembly includes a first insulating block, a pair of first signal terminals, and a first shielding shell. Each first shielding shell has a first shielding side surface exposed to the first side. Each first spoke is in mechanical contact with the first shielding shells of a same electrical module, and each second spoke is in contact with the first shielding side surface of the corresponding first shielding shell, thus achieving conduction between the first shielding shells and the first grounding member.
    Type: Application
    Filed: January 25, 2022
    Publication date: August 4, 2022
    Inventors: Zhi Li He, Wen Chang Chang, Jie Liao, Jin Zhu Wang
  • Patent number: 11404019
    Abstract: The present disclosure provides a method for compensating a common voltage. The method for compensating a common voltage includes: generating a feedback signal by acquiring a real-time monitoring result of a feedback signal line on the common voltage, the feedback signal including a plurality of time periods, each of the time periods including a first sub-period in which the feedback signal is interfered by the periodic signal and a second sub-period in which the feedback signal is not interfered by the periodic signal; processing the feedback signal to eliminate distortion of the feedback signal caused by interference of the periodic signal in the first sub-period; and compensating for the common voltage according to the feedback signal.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: August 2, 2022
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xinmao Qiu, Zongxiang Li, Jiamin Liao, Jin Wang, Hao Cheng, Yao Liu, Min Zhou, Wenchang Tao, Zhendian Wu, Zuwen Liu, Guichun Hong, Zihua Zhuang, Yaochao Lv, Changhong Shi, Linlin Lin, Wen Zha, Jingguang Zhu, Jiantao Lin, Hongjiang Wu
  • Patent number: 11402157
    Abstract: An evaporator suitable for a thermal dissipation module. The thermal dissipation module includes a tube or pipe and fluid. The evaporator includes a housing, a first heat dissipation structure and a second heat dissipation structure disposed in a sealed chamber of the housing. The chamber is configured to communicate with the pipe, and the fluid is configured to flow in the pipe and the chamber. The first heat dissipation structure and a second heat dissipation structure provide a plurality of fluid flow passages through which the fluid flows and evaporates. A manufacturing method of the evaporator is also disclosed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 2, 2022
    Inventors: Yung-Chih Wang, Cheng-Wen Hsieh, Wen-Neng Liao, Jau-Han Ke
  • Patent number: 11397302
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: July 26, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20220230963
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
  • Publication number: 20220223464
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220216106
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Patent number: 11379021
    Abstract: A heat dissipation module suitable for an electronic device is provided. The electronic device has a heat source. The heat dissipation module includes an evaporator and a pipe assembly. An internal space of the evaporator is divided into a first space and a second space, and the heat source is thermally contacted with the second space. The pipe assembly is connected to the evaporator to form a loop. A working fluid is filled in the loop. The working fluid in liquid receiving heat from the heat source is transformed into vapor and flows to the pipe assembly. Then, the working fluid in vapor is transformed into liquid by dissipating heat in the pipe assembly and flows to the first space of the evaporator. The working fluid in liquid is stored in the first space and is used for supplying to the second space.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: July 5, 2022
    Assignee: Acer Incorporated
    Inventors: Yung-Chih Wang, Cheng-Wen Hsieh, Wen-Neng Liao
  • Publication number: 20220204936
    Abstract: A non-fibrous film of which the composition includes a collagen and a polyester polymer is provided. A content of the polyester polymer in the non-fibrous film is 1-60 wt %. Moreover, the non-fibrous film has a swelling rate of 1-200 ?m/hour or a swelling proportion per unit time of 0.1-2%/hour in an aqueous liquid.
    Type: Application
    Filed: September 15, 2021
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Bing LIOU, Chih-Ching LIAO, Hsin-Yi HSU, Ying-Wen SHEN, Yun-Chung TENG, Hsin-Hsin SHEN, Yi-Chen CHEN
  • Patent number: 11374099
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: June 28, 2022
    Inventors: Ting-Feng Liao, Sheng-Hong Chen, Kuang-Wen Liu
  • Patent number: 11367591
    Abstract: A plasma-processing apparatus includes a chamber, a plasma generator, and a composite plasma modulator. The chamber includes a plasma zone. The plasma generator is configured to generate a plasma in the plasma zone. The composite plasma modulator is configured to modulate the plasma. The composite plasma modulator includes a dielectric plate made of a first dielectric material and a first modulating portion made of a second dielectric material and coupled to the dielectric plate.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 21, 2022
    Inventor: Han-Wen Liao
  • Publication number: 20220168213
    Abstract: Disclosed herein is a water-in-oil emulsion composition that includes, based on the total weight of the water-in-oil emulsion composition, 2 wt % to 10 wt % of Avena sativa kernel oil, 15 wt % to 38 wt % of octyldodecanol, and water. The water-in-oil emulsion composition is free from a surfactant and a gelling agent.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 2, 2022
    Inventors: Yi-Wen LIAO, Jie LI
  • Publication number: 20220162452
    Abstract: A material may include a pigment and one or more silicon oxycarbides (SiOC) disposed in the black ceramic pigment, wherein a surface of the pigment is free of one or more silanols (Si—OH) bonds.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 26, 2022
    Applicant: Melior Innovations, Inc.
    Inventors: Wen Liao, Connor Kilgallen, Isabel Burlingham, David Bening, Paul Lindquest
  • Publication number: 20220157889
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20220150190
    Abstract: A method and system for recommending content using a chatbot are provided. The content recommendation method includes calling a chatbot to a chatroom based on a first user interaction with the chatroom; providing first content corresponding to a second user interaction with the chatroom while the chatbot is in the chatroom; and recommending second content related to the first content.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 12, 2022
    Inventors: Li-Wen LIAO, Yun-RU Sun, Chan-Yuan Chang, Jun-Wei Wan
  • Publication number: 20220129914
    Abstract: The present invention provides a method for verifying a product authenticity with fabric features, comprising steps of receiving at least one fabric partial image and performing image analysis to determine an image optical feature distribution information of an anti-counterfeiting feature, receiving a fabric serial number generated by operation of an input device, and determining whether a fabric is an authorized product by using the fabric serial number or the information.
    Type: Application
    Filed: January 6, 2021
    Publication date: April 28, 2022
    Inventors: Chih-Wen LIAO, Chu WU, Yuh-Jiun LIN, Chi-Hang TSAI, Han-Chao LEE, Ko-Yang WANG
  • Patent number: 11315861
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11316096
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Patent number: 11306363
    Abstract: A microRNA (miRNA) expression signature for predicting triple-negative breast cancer (TNBC) recurrence is provided. The miRNA expression signature consists essentially of hsa-miR-139-5p, hsa-miR-10b-5p, hsa-miR-486-5p, hsa-miR-455-3p, hsa-miR-107, hsa-miR-146b-5p, hsa-miR-324-5p, and hsa-miR-20a-5p.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 19, 2022
    Inventors: Kuang-Wen Liao, Hsien-Da Huang, Hsiao-Chin Hong, Cheng-Hsun Chuang