Abstract: The present disclosure provides an electronic package. The electronic package includes an antenna structure having a first antenna and a second antenna at least partially covered by the first antenna. The electronic package also includes a directing element covering the antenna structure. The directing element has a first portion configured to direct a first electromagnetic wave having a first frequency to transmit via the first antenna and a second portion configured to direct a second electromagnetic wave having a second frequency different from the first frequency to transmit via the second antenna. A method of manufacturing an electronic package is also provided.

Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Abstract: A memory structure includes a substrate, a barrier layer, an etch stop layer, a bottom electrode, a data storage feature and a top electrode. The substrate has a metal trench. The barrier layer is disposed over the metal trench. The etch stop layer surrounds the barrier layer, and, together with the barrier layer, completely covers the metal trench. The bottom electrode is disposed over the barrier layer. The data storage feature is disposed over the bottom electrode. The top electrode is disposed over the data storage feature.

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: An active device substrate includes an active device and an electrode. The electrode includes a first light shielding conductive pattern, a second light shielding conductive pattern, a third light shielding conductive pattern, and a first metal oxide protection pattern. The first light shielding conductive pattern, the second light shielding conductive pattern, and the third light shielding conductive pattern are sequentially stacked to form a conductive stack. The conductive stack is disposed in an opening of the first metal oxide protection pattern. A first portion, a second portion, and a third portion of the first metal oxide protection pattern respectively contact a sidewall of the first light shielding conductive pattern, a sidewall of the second light shielding conductive pattern, and a sidewall of the third light shielding conductive pattern. Materials of the first portion, the second portion, and the third portion of the first metal oxide protection pattern are the same.

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

Abstract: An integrated circuit structure includes a plurality of transistors, an interconnect layer, and a memory stack. The interconnect layer includes an interlayer dielectric (ILD) and a conductive structure embedded in the ILD. The conductive structure includes a barrier layer and a conductive filling material surrounded by the barrier layer in a cross-sectional view. The memory stack is over the interconnect layer. The memory stack includes a bottom electrode extending across the conductive structure in the cross-sectional view, a resistance switching layer over the bottom electrode, and a top electrode over the resistance switching layer. In the cross-sectional view, an interface formed by the bottom electrode and the barrier layer has a topmost point higher than a topmost point of an interface formed by the bottom electrode and the conductive filling material.

Abstract: A display panel includes a driving backplane, a light emitting component, a reflective structure and a bridging component. The driving backplane has a first pad and a second pad separated from each other. The light emitting component has a first electrode and a second electrode. The first electrode is electrically connected to the first pad of the driving backplane, and the first electrode is located between the second electrode and the first pad of the driving backplane. The reflective structure is disposed on the driving backplane and located at a periphery of the light emitting component. The bridging component is disposed on the light emitting component. One end of the bridging component is electrically connected to the second electrode. The bridging component passes across at least one portion of the reflective structure. The other end of the bridging component is electrically connected to the second pad of the driving backplane.

Abstract: A wet etch apparatus includes a wafer chuck, a dispensing nozzle, a liquid etchant container, and an electric field generator. The dispensing nozzle is above the wafer chuck. The liquid etchant container is in fluid communication with the dispensing nozzle. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator includes a first electrode and a second electrode spaced apart from the first electrode in a direction substantially perpendicular to a top surface of the wafer chuck, and the second electrode is an electrode plate above the wafer chuck.

Abstract: A method for manufacturing a semiconductor device includes: forming an etch stop layer with an opening; forming a barrier layer on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion to be inserted into the opening of the etch stop layer; forming a bottom electrode layer on the layer portion of the barrier layer opposite to the etch stop layer; forming a ferroelectric layer on the bottom electrode layer opposite to the barrier layer; and forming a top electrode layer on the ferroelectric layer opposite to the bottom electrode layer.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material on a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. The bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.

Abstract: A water filter includes a filtering head, a filter bottle assembly, a switch member, and a quick release device. The filtering head includes a flow channel module. The filter bottle assembly includes a filter bottle. The quick release device includes a press lever, two links, and two push members. When the press lever is pivoted, the two links and the two push members are driven by the press lever to move the filter bottle simultaneously so that the filter bottle is mounted on or detached from the filtering head quickly. A switch member functions as a waterway switch to control a water supply of the filtering head and functions as a locking mechanism for locking or unlocking the quick release device.

Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

Abstract: A window arrangement method includes the following steps. The method obtains the first program identifier of a foreground window. The method determines whether the first program identifier belongs to a preset identifier. In response to the first program identifier belonging to the preset identifier, the method obtains the first handle and the first window data of the foreground window and sets the application handle of a window arrangement application as the parent window handle of the first handle. The first toolbar or the first address bar of the foreground window is removed through the window arrangement application to generate a first simplified window. Moreover, the first simplified window is displayed in a window of the window arrangement application through the window arrangement application according to the first window data and the first default window position.

Abstract: A circuit board includes a plurality of pixel areas. Each pixel area includes a plurality of electrode pad groups. The electrode pad groups are arranged in a first direction. Each of the electrode pad groups includes a first electrode pad, a second electrode pad, and a third electrode pad. The first electrode pad, the second electrode pad, and the third electrode pad are arranged in a second direction. The second direction is different from the first direction. The first electrode pad is disposed between the second electrode pad and the third electrode pad. The first electrode pad is configured to provide a first voltage potential. The second electrode pad and the third electrode pad are configured to provide a second voltage potential. The first voltage potential is different from the second voltage potential.

Abstract: The present invention provides novel pharmaceutical formulations comprising derivatives of NDGA, including M4N (tetra-0-methyl nordihydroguaiaretic acid) and temozolomide and their use in the inhibition and treatment of neoplastic diseases, including glioblastoma multiforme, lung and other cancers.

Abstract: A battery module is provided. The battery module includes a front lid having a fluid inlet for flowing a fluid into the battery module and a battery case coupled to the front lid and having an accommodation region for accommodating battery cells. The battery case further includes a case frame, one or more inlet channels, and one or more outlet channels. Each of the one or more inlet channels receiving the fluid from the fluid inlet and going through the case frame for flowing the fluid through the battery case further includes one or more inlet slits for flowing the fluid into the accommodation region for cooling the battery cells. Each of the one or more outlet channels going through the case frame for flowing the fluid through the battery case is coupled to the accommodation region for flowing the fluid out of a fluid outlet of the battery module.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.