Abstract: An ?-aminoketone-containing polyfunctionalized macromolecular photoinitiator, which is prepared from a double-bond-containing ?-aminoketone micromolecular photoinitiator A and a polythiol compound B through thiol-ene click reaction. A preparation of the ?-aminoketone-containing polyfunctionalized macromolecular photoinitiator and an application of the ?-aminoketone-containing polyfunctionalized macromolecular photoinitiator in the radiation curing are also provided.

Abstract: A method and system for recommending content using a chatbot are provided. The content recommendation method includes calling a chatbot to a chatroom based on a first user interaction with the chatroom; providing first content corresponding to a second user interaction with the chatroom while the chatbot is in the chatroom; and recommending second content related to the first content.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.

Abstract: A method for predicting a prognosis of a gastric cancer patient is provided, including measuring expression levels of five RNAs in a sample of the gastric cancer patient, and the five RNAs being ANTXR1, COL6A3, THBS2, THBS4, and SFRP4; and comparing the expression levels of the five RNAs in the sample with expression levels of the five RNAs in a control, in which the gastric cancer patient is identified as having a poor prognosis when the expression levels of the five RNAs in the sample are lower than the expression levels of the five RNAs in the control.

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: A user interface synchronous scrolling method includes: opening a plurality of user interfaces, obtaining a scrolling parameter through the input-output interface; and judging whether the application program corresponding to each user interface belongs to a software support mode. By determining whether the application program corresponding to each user interface belongs to the software support mode, and providing corresponding control steps, the effect of synchronous scrolling for multiple user interfaces is achieved.

Abstract: A window arrangement method includes the following steps. The method obtains the first program identifier of a foreground window. The method determines whether the first program identifier belongs to a preset identifier. In response to the first program identifier belonging to the preset identifier, the method obtains the first handle and the first window data of the foreground window and sets the application handle of a window arrangement application as the parent window handle of the first handle. The first toolbar or the first address bar of the foreground window is removed through the window arrangement application to generate a first simplified window. Moreover, the first simplified window is displayed in a window of the window arrangement application through the window arrangement application according to the first window data and the first default window position.

Abstract: The present invention discloses a smart clothing and its device mount, wherein the device mount includes an upper casing and a lower casing, a circuit board is arranged between the upper casing and the lower casing, and a metal contact of the top surface of the circuit board penetrates through the upper casing to form a plurality of metal contact points, and the cable interface of the bottom surface of the circuit board passes through the lower casing, and the bottom surface of the lower casing is formed with individual cable grooves toward each cable interface for guiding the transmission wire to insert into the cable interface along the cable groove, and the device mount is combined with a soft gasket on the clothing body and is equipped with a waterproof protective layer to avoid damage to the circuit components and transmission wire during cleaning; when the device mount is installed with the electronic device, the motion status can be monitored.

Abstract: A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: An apparatus for removing a photoresist layer from at least one alignment mark of a wafer is provided. The apparatus includes a holder, a solvent dispenser, and a suction unit. The holder is used to support the wafer, wherein the alignment mark is formed in a peripheral region of the wafer. The solvent dispenser is used to spray a solvent onto the photoresist layer on the alignment mark of the wafer to generate a dissolved photoresist layer. The suction unit is used to remove the dissolved photoresist layer and the solvent from the wafer through exhausting.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A circuit board structure for a display device includes a substrate, a bump, a protective layer, and a moisture-resistant layer. The substrate includes a first surface and a second surface opposite to the first surface. The bump is disposed on the first surface of the substrate and includes a first inorganic material. The protective layer is disposed on the first surface of the substrate. The protective layer includes an organic material and a first opening, in which the bump is positioned in the first opening. The moisture-resistant layer entirely covers the protective layer. The moisture-resistant layer includes a second inorganic material and a second opening, in which a portion of the bump is exposed in the second opening.

Abstract: A display panel includes a substrate, an LED array disposed on the front side of the substrate, a driving circuit disposed on the front side of the substrate and connected to the LED array, a connecting line and a transparent conductive layer disposed on the back side of the substrate. The connecting line is spaced apart with a side surface of the substrate thereby defining a cutting area. The transparent conductive layer extends from the cutting area and at least partially covering the connecting line. The display panel further includes a first passivation layer and a conductive layer. The first passivation layer is disposed on the transparent conductive layer and the connecting line. The side surfaces of the first passivation layer, the transparent conductive layer, and the substrate are aligned. The conductive layer penetrates the first passivation layer to connect the transparent conductive layer to the driving circuit.

Abstract: An equipment detection system includes a processor, a communication module, and a display module. The processor is configured to detect a connection to an external device. The processor enumerates device information about the external device, obtains user information from a local host, and generates a data structure according to the device information and the user information. The processor is included in the local host. The communication module is configured to transmit the data structure and receive status information. The status information includes a placement space corresponding to the external device or the status of the external device. The status information is associated with the data structure. Moreover, the display module is configured to display the status information.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.