Abstract: A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.

Abstract: An apparatus for removing a photoresist layer from at least one alignment mark of a wafer is provided. The apparatus includes a holder, a solvent dispenser, and a suction unit. The holder is used to support the wafer, wherein the alignment mark is formed in a peripheral region of the wafer. The solvent dispenser is used to spray a solvent onto the photoresist layer on the alignment mark of the wafer to generate a dissolved photoresist layer. The suction unit is used to remove the dissolved photoresist layer and the solvent from the wafer through exhausting.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A display panel includes a substrate, an LED array disposed on the front side of the substrate, a driving circuit disposed on the front side of the substrate and connected to the LED array, a connecting line and a transparent conductive layer disposed on the back side of the substrate. The connecting line is spaced apart with a side surface of the substrate thereby defining a cutting area. The transparent conductive layer extends from the cutting area and at least partially covering the connecting line. The display panel further includes a first passivation layer and a conductive layer. The first passivation layer is disposed on the transparent conductive layer and the connecting line. The side surfaces of the first passivation layer, the transparent conductive layer, and the substrate are aligned. The conductive layer penetrates the first passivation layer to connect the transparent conductive layer to the driving circuit.

Abstract: A circuit board structure for a display device includes a substrate, a bump, a protective layer, and a moisture-resistant layer. The substrate includes a first surface and a second surface opposite to the first surface. The bump is disposed on the first surface of the substrate and includes a first inorganic material. The protective layer is disposed on the first surface of the substrate. The protective layer includes an organic material and a first opening, in which the bump is positioned in the first opening. The moisture-resistant layer entirely covers the protective layer. The moisture-resistant layer includes a second inorganic material and a second opening, in which a portion of the bump is exposed in the second opening.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: An equipment detection system includes a processor, a communication module, and a display module. The processor is configured to detect a connection to an external device. The processor enumerates device information about the external device, obtains user information from a local host, and generates a data structure according to the device information and the user information. The processor is included in the local host. The communication module is configured to transmit the data structure and receive status information. The status information includes a placement space corresponding to the external device or the status of the external device. The status information is associated with the data structure. Moreover, the display module is configured to display the status information.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

Abstract: A method for forming an anti-counterfeiting feature during knitting of a fabric and a fabric thereof, the fabric is knitted with at least one first yarn, a part of the fabric includes a plurality of featured yarn loops formed by a second yarn, the featured yarn loops constitute an anti-counterfeiting feature, the anti-counterfeiting feature can be directly observed from one side surface of the fabric, the second yarn is formed by twisting at least two sub-yarns with different shades, and shades of the at least two sub-yarns and the first yarn are different from each other, and a shade of the featured yarn loops displayed on the side surface is random. Accordingly, the randomness of yarn twisting makes the anti-counterfeiting feature difficult to be replicated, thereby preventing unscrupulous manufacturers from counterfeiting the fabric.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.

Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.

Abstract: The present disclosure relates to an electronic device, a method, and a computer-readable recording medium for electronic transactions. The electronic device displays a first graphical user interface (GUI) on a touch screen, the first GUI including a currency amount, displays a second GUI corresponding to transmission of the currency amount according to a currency transmission signal input to the touch screen, determines an amount of an electronic transaction according to the currency transmission signal, and transmits a generated signal containing information on the amount of the electronic transaction to an information processing system.

Abstract: Methods, apparatus and systems using heat exchanger reactors to form polymer derived ceramic materials, including methods for making polysilocarb (SiOC) precursors.

Abstract: A heat dissipating module includes a heat dissipating substrate, a first structural plate, and a first heat conductive plate. The heat dissipating substrate has an inlet, an outlet, and a first container formed on a top surface of the heat dissipating substrate. The inlet and the outlet are communicated with the first container respectively. The first structural plate has a first channel member and is contained in the first container. The first channel member is communicated with the inlet and the outlet respectively. Heat dissipating liquid flows through the first channel member via the inlet, and flows out of the heat dissipating module via the outlet. The first heat conductive plate covers the first structural plate. The first heat conductive plate is in contact with a heat generating member for conducting heat energy generated by the heat generating member to the heat dissipating liquid.