Patents by Inventor Wen Liao

Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120640
    Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a carrier, an antenna element and a cladding element. The carrier defines a first area and a second area adjacent to the first area. The antenna element is in the first area. The cladding element covers the antenna element and is configured for enhancing antenna gain of the antenna element. The second area is exposed from the cladding element and is distant from the antenna element.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jenchun CHEN, Ya-Wen LIAO
  • Publication number: 20240114810
    Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 4, 2024
    Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
  • Publication number: 20240085185
    Abstract: Embodiments are disclosed for submersion detection and underwater depth and low-latency temperature estimation. In an embodiment, a method comprises: determining a first set of vertical accelerations obtained from an inertial sensor of a wearable device; determining a second set of vertical accelerations obtained from pressure data; determining a first feature associated with a correlation between the first and second sets of vertical accelerations; and determining that the wearable device is submerged or not submerged in water based on a machine learning model applied to the first feature. In another embodiment, a method comprises: determining a submersion state of a wearable device; and responsive to the submersion state being submerged, computing a forward estimate of water temperature based on measured ambient water temperature at the water surface, a temperature error lookup table, and a rate of change of the ambient water temperature.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 14, 2024
    Inventors: Stephen P. Jackson, Ti-Yen Lan, Yi Wen Liao, Alexandru Popovici, Igor Tchertkov, Rose M. Wahlin, Natisa Jeyakanthan, Amit K. Jain, Kenneth M. Lee
  • Publication number: 20240075895
    Abstract: Embodiments are disclosed for crash detection on one or more mobile devices (e.g., smartwatch and/or smartphone). In some embodiments, a method comprises: detecting, with at least one processor, a crash event on a crash device; extracting, with the at least one processor, multimodal features from sensor data generated by multiple sensing modalities of the crash device; computing, with the at least one processor, a plurality of crash decisions based on a plurality of machine learning models applied to the multimodal features; and determining, with the at least one processor, that a severe vehicle crash has occurred involving the crash device based on the plurality of crash decisions and a severity model.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Vinay R. Majjigi, Sriram Venkateswaran, Aniket Aranake, Tejal Bhamre, Alexandru Popovici, Parisa Dehleh Hossein Zadeh, Yann Jerome Julien Renard, Yi Wen Liao, Stephen P. Jackson, Rebecca L. Clarkson, Henry Choi, Paul D. Bryan, Mrinal Agarwal, Ethan Goolish, Richard G. Liu, Omar Aziz, Alvaro J. Melendez Hasbun, David Ojeda Avellaneda, Sunny Kai Pang Chow, Pedro O. Varangot, Tianye Sun, Karthik Jayaraman Raghuram, Hung A. Pham
  • Patent number: 11894267
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei Chen, Fu-Ting Sung, Yu-Wen Liao, Wen-Ting Chu, Fa-Shen Jiang, Tzu-Hsuan Yeh
  • Publication number: 20240034641
    Abstract: A water filter includes a filtering head, a filter bottle assembly, a switch member, and a quick release device. The filtering head includes a flow channel module. The filter bottle assembly includes a filter bottle. The quick release device includes a press lever, two links, and two push members. When the press lever is pivoted, the two links and the two push members are driven by the press lever to move the filter bottle simultaneously so that the filter bottle is mounted on or detached from the filtering head quickly. The a switch member functions as a waterway switch to control a water supply of the filtering head and functions as a locking mechanism for locking or unlocking the quick release device.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventors: Sheng-Nan Lin, Hao-Chan Wei, Yi-Wen Liao, Zhe-Hua Ou
  • Patent number: 11889705
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: January 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11888210
    Abstract: The present disclosure provides an electronic package. The electronic package includes an antenna structure having a first antenna and a second antenna at least partially covered by the first antenna. The electronic package also includes a directing element covering the antenna structure. The directing element has a first portion configured to direct a first electromagnetic wave having a first frequency to transmit via the first antenna and a second portion configured to direct a second electromagnetic wave having a second frequency different from the first frequency to transmit via the second antenna. A method of manufacturing an electronic package is also provided.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, Ya-Wen Liao
  • Patent number: 11862855
    Abstract: The present disclosure provides an antenna module including a substrate, a first antenna disposed on the substrate and a second antenna disposed on the substrate and spaced apart from the first antenna. The first antenna is configured to have a first operating frequency and the second antenna is configured to have a second operating frequency different from the first operating frequency. The antenna module further includes an element configured to focus an electromagnetic wave transmitted or received by the first antenna and the second antenna. A semiconductor device package is also disclosed.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: January 2, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, Ya-Wen Liao
  • Patent number: 11856797
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20230410128
    Abstract: A method for managing a genuine fabric with blockchain data comprises the following steps: receiving at least one image of a genuine fabric photographed by a computing device, wherein the image contains at least one anti-counterfeiting texture generated during a manufacturing process thereof, and the computing device performs image analysis on the anti-counterfeiting texture to obtain at least one hash value; forming an smart contract with a text serial number corresponding to the genuine fabric and the hash value by one of a plurality of nodes in a blockchain through the computing device, and launching the smart contract to the nodes; and providing a key to at least one of a fabric production end and a brand sales end, wherein after the smart contract is signed, a non-fungible token which is associated with the genuine fabric is minted at one of the nodes in the blockchain.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 21, 2023
    Inventor: Chih-Wen LIAO
  • Patent number: 11848480
    Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a carrier, an antenna element and a cladding element. The carrier defines a first area and a second area adjacent to the first area. The antenna element is in the first area. The cladding element covers the antenna element and is configured for enhancing antenna gain of the antenna element. The second area is exposed from the cladding element and is distant from the antenna element.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, Ya-Wen Liao
  • Patent number: 11844286
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Patent number: 11839090
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11832529
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Publication number: 20230380190
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Fei CHIU, Wen-Ting CHU, Yong-Shiuan TSAIR, Yu-Wen LIAO, Chih-Yang CHANG, Chin-Chieh YANG
  • Publication number: 20230371396
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Publication number: 20230365756
    Abstract: An ?-aminoketone-containing polyfunctionalized macromolecular photoinitiator, which is prepared from a double-bond-containing ?-aminoketone micromolecular photoinitiator A and a polythiol compound B through thiol-ene click reaction. A preparation of the ?-aminoketone-containing polyfunctionalized macromolecular photoinitiator and an application of the ?-aminoketone-containing polyfunctionalized macromolecular photoinitiator in the radiation curing are also provided.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Ming JIN, Wen LIAO, Feng GUO, Jingdong LI, Chengshuang YANG, Lidong LIN, Bin FAN
  • Patent number: D1023920
    Type: Grant
    Filed: April 11, 2021
    Date of Patent: April 23, 2024
    Assignee: GUANGDONG GOPOD GROUP CO., LTD.
    Inventor: Zhuo-Wen Liao
  • Patent number: D1023922
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: April 23, 2024
    Assignee: GUANGDONG GOPOD GROUP CO., LTD.
    Inventor: Zhuo-Wen Liao