Patents by Inventor Wen Liao

Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermal chemical vapor deposition system and operating method thereof
    Patent number: 10724140
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Method to form memory cells separated by a void-free dielectric structure
    Patent number: 10714536
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Hardware boost method and hardware boost system
    Patent number: 10706497
    Abstract: A hardware boost method and a hardware boost system are provided. The hardware boost method includes: initializing a status table, wherein the status table includes multiple statuses, each of the statuses corresponds to a first action and a second action, and each of the statuses includes FPS information; and in each episode: determining that a system status belongs to a first status among the statuses; executing one of the first action and the second action according to a value corresponding to the first status and the first action and a value corresponding to the first status and the second action to enter a second status among the statuses and obtain a reward value; and refreshing the value corresponding to the first status and the one of the first action and the second action according to the reward value.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Wistron Corporation
    Inventors: Li-Yu Yang, Fang-Wen Liao, Ping-Hung Chen
  • RRAM cell structure with laterally offset BEVA/TEVA
    Patent number: 10700275
    Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Memory device
    Patent number: 10686125
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • PACKAGING STRUCTURE WITH GROOVE
    Publication number: 20200185631
    Abstract: A packaging structure with groove includes a substrate, a lower conductive layer, an optical element, a sealing layer and a barrier layer. The lower conductive layer is arranged on one face of the substrate. The optical element is arranged on one face of the lower conductive layer. The upper conductive layer is arranged on one face of the optical element. The packaging structure further comprises a groove defined on an inactive area of the optical element. The sealing layer is arranged on one face of the optical element and on one face of the upper conductive layer. The barrier layer is arranged on one face of the sealing layer. Because the groove is formed on inactive area of the optical element to enhance lateral sealing tightness, extended interface is provided between sealing layer/barrier layer and the substrate, thus enhance the water-resistant and gas-resistant property for package.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 11, 2020
    Inventors: Shih-Wen LIAO, Yu-Yang CHANG
  • RRAM memory cell with multiple filaments
    Patent number: 10680038
    Abstract: In some embodiments, the present disclosure relates to a method of forming a memory circuit. The method may be performed by forming an interconnect wire within an inter-level dielectric (ILD) layer over a substrate. A conjunct electrode structure is formed over the interconnect wire, a data storage film is formed over the conjunct electrode structure, and a disjunct electrode structure is formed over the data storage film. The data storage film, the disjunct electrode structure, and the conjunct electrode structure are patterned to form a first data storage layer between the interconnect wire and a first disjunct electrode and to form a second data storage layer between the interconnect wire and a second disjunct electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • WET ETCH APPARATUS AND METHOD FOR USING THE SAME
    Publication number: 20200168480
    Abstract: A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.
    Type: Application
    Filed: August 15, 2019
    Publication date: May 28, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hong-Ting LU, Han-Wen LIAO
  • WET ETCH APPARATUS AND METHOD OF USING THE SAME
    Publication number: 20200168479
    Abstract: A method includes dispensing a chemical solution including charged ions onto a semiconductor substrate to chemically etch a target structure on the semiconductor substrate, and applying an electric field on the semiconductor substrate during dispensing the chemical solution on the semiconductor substrate, such that the charged ions in the chemical solution are moved in response to the electric field.
    Type: Application
    Filed: June 11, 2019
    Publication date: May 28, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hong-Ting LU, Han-Wen LIAO
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200161188
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.
    Type: Application
    Filed: May 30, 2019
    Publication date: May 21, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen LIAO
  • PLASMA PROCESSING APPARATUS AND MANUFACTURING METHOD USING THE SAME
    Publication number: 20200161102
    Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.
    Type: Application
    Filed: July 24, 2019
    Publication date: May 21, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen LIAO
  • METHOD FOR FORMING A HOMOGENEOUS BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE FOR MEMORY
    Publication number: 20200144172
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • METHOD TO FORM MEMORY CELLS SEPARATED BY A VOID-FREE DIELECTRIC STRUCTURE
    Publication number: 20200127053
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Application
    Filed: February 4, 2019
    Publication date: April 23, 2020
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • METHOD FOR USING INTERCOM TO PERFORM INTELLIGENT CALLING PROCESS, INTELLIGENT CALLING APPARATUS AND SYSTEM THEREOF
    Publication number: 20200112633
    Abstract: A method for using an intercom to implement an intelligent calling process, an intelligent calling apparatus and a system is presented. The method is adapted to a site that adopts intercoms to perform a calling process. The system utilizes a server for receiving a calling signal generated by an intelligent calling apparatus. The calling signal records ID information used to represent a calling location. The server obtains the calling location by querying a database. The software process running in the server combines voice signals according to the calling location. A calling voice is generated and sent to the intercoms carried by the personnel member. When any personnel members receive the calling voice by the intercom, this calling process can be completed as the personnel member arrives at the calling location.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: LI-WEN LIAO, WAN-CHEN CHEN, YEN-TING HO
  • INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY
    Publication number: 20200098828
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT
    Publication number: 20200098983
    Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Resistive Switching Random Access Memory with Asymmetric Source and Drain
    Publication number: 20200083294
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Monoclonal antibody inhibiting immunosuppressive functions of pathogens, antigen-binding fragment thereof, and hybridomas producing such antibody
    Patent number: 10577409
    Abstract: The present invention relates to a monoclonal antibody that inhibits immunosuppressive functions of pathogens, antigen-binding fragment thereof, and hybridomas producing such antibody. The monoclonal antibody or antigen-binding fragment thereof bind to a peptide consisting an amino acid sequence represented by MEKVGKDGVITVE (SEQ ID NO: 1). The present invention also discloses use of the invented monoclonal antibody or antigen-binding fragment thereof, and method of preparation for such hybridomas.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 3, 2020
    Assignee: SAGABIO CO., LTD.
    Inventors: Kuang-Wen Liao, Yu-Ling Lin, Ting-Yan Jian
  • METHOD, APPARATUS AND SYSTEM FOR INTELLIGENT CALLING SERVICE
    Publication number: 20200068370
    Abstract: The disclosure is related to a method for intelligent calling service, an apparatus and a system thereof. The method is performed in a server. When the server receives a service request signal recording a device ID generated by an apparatus for intelligent calling service, call information of service personnel can be obtained based on a service location corresponding to the device ID by querying a database of the server. After that, the server issues a service call signal to service communication devices carried by the service personnel. When a distance between the service communication device and the apparatus for intelligent calling service reaches a threshold, it shows that one of the service personnel is in service. This calling service procedure is done when the server receives a dismissing signal generated by the apparatus or the service communication device near the apparatus.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: LI-WEN LIAO, YEN-TING HO, WAN-CHEN CHEN
  • PORTABLE ELECTRONIC DEVICE AND METHOD OF CONTROLLING AN IMAGE OF A DISPLAY MODULE
    Publication number: 20200064889
    Abstract: A portable electronic device is provided and includes a first display module, a second display module, a keyboard device, a sensing unit and a control unit. The second display module is pivotally connected to the first display module. The sensing unit is configured to sense a position of the keyboard device relative to the second display module to output a sensing signal. The control unit is configured to control a displaying image of the second display module according to the sensing signal.
    Type: Application
    Filed: November 20, 2018
    Publication date: February 27, 2020
    Inventors: Chen Yi LIANG, Keng-Hsien YANG, Hsin Ting HO, Cheng-Wei CHANG, Fang-Wen LIAO