Abstract: A heat dissipating module includes a heat dissipating substrate, a first structural plate, and a first heat conductive plate. The heat dissipating substrate has an inlet, an outlet, and a first container formed on a top surface of the heat dissipating substrate. The inlet and the outlet are communicated with the first container respectively. The first structural plate has a first channel member and is contained in the first container. The first channel member is communicated with the inlet and the outlet respectively. Heat dissipating liquid flows through the first channel member via the inlet, and flows out of the heat dissipating module via the outlet. The first heat conductive plate covers the first structural plate. The first heat conductive plate is in contact with a heat generating member for conducting heat energy generated by the heat generating member to the heat dissipating liquid.

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

Abstract: Methods, apparatus and systems using heat exchanger reactors to form polymer derived ceramic materials, including methods for making polysilocarb (SiOC) precursors.

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.

Abstract: A method includes dispensing a chemical solution including charged ions onto a semiconductor substrate to chemically etch a target structure on the semiconductor substrate, and applying an electric field on the semiconductor substrate during dispensing the chemical solution on the semiconductor substrate, such that the charged ions in the chemical solution are moved in response to the electric field.

Abstract: A composite photovoltaic structure having the following components is illustrated. A first photovoltaic unit is disposed on a transparent substrate, and electrically connected to a second photovoltaic unit in parallel, and the second photovoltaic unit is stacked on the first photovoltaic unit. The first photovoltaic unit is disposed on a second transparent electrode layer, and a first transparent conductive layer is disposed on a top of the first photovoltaic unit and electrically connected to a first transparent electrode layer, and the second photovoltaic unit is disposed on the first transparent conductive layer. A second transparent conductive layer is disposed on the second photovoltaic unit and is electrically connected to the second transparent electrode layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.

Abstract: A manufacturing method of a composite photovoltaic structure including a step of forming a transparent electrode material, a step of forming a first photovoltaic unit, a step of forming a first insulation layer, a step of forming a first transparent conductive layer, a step of forming a second photovoltaic unit, a step of forming a second insulation layer, a step of forming a second transparent conductive layer and a step of splitting a product. Thus, the manufacturing method of the composite photovoltaic structure has a photoelectric reaction area of a significantly improved omnidirectional concentration gain, an efficiently induced current and a low manufacturing cost, without affecting the whole structure thickness.

Abstract: A liquid-cooled heat dissipation device is disclosed, comprising a main body, a centrifugal pump, an inlet pipe and an outlet pipe. The main body comprises liquid flow channels and liquid storage tanks. The liquid flow channels are circumferentially arranged and spaced apart. The liquid storage tanks are located on both sides of the main body, and the liquid storage tanks on the same side are connected by liquid flow channels. The centrifugal pump is installed in one of the liquid storage tanks. The inlet pipe and the outlet pipe are in spatial communication with the other two liquid storage tanks, respectively. The centrifugal pump guides a cooling liquid through the inlet pipe, main body and outlet pipe. The cooling liquid travel through the liquid storage tanks via the liquid flow channels and forms radial jet flows after being pumped by centrifugal pump.

Abstract: A packaging structure with groove includes a substrate, a lower conductive layer, an optical element, a sealing layer and a barrier layer. The lower conductive layer is arranged on one face of the substrate. The optical element is arranged on one face of the lower conductive layer. The upper conductive layer is arranged on one face of the optical element. The packaging structure further comprises a groove defined on an inactive area of the optical element. The sealing layer is arranged on one face of the optical element and on one face of the upper conductive layer. The barrier layer is arranged on one face of the sealing layer. Because the groove is formed on inactive area of the optical element to enhance lateral sealing tightness, extended interface is provided between sealing layer/barrier layer and the substrate, thus enhance the water-resistant and gas-resistant property for package.

Abstract: Optical additive manufacturing, including laser additive manufacturing systems, apparatus and methods using polymer derived ceramic build materials. Additive manufacturing build materials are made of polymer derived ceramic including SiOC, precures, cured materials, hard cured materials, and pyrolized materials. Polymer derived ceramic build materials are mixed with and used in conjunction with other build materials.

Abstract: The present disclosure relates to an electronic device, a method, and a computer-readable recording medium for electronic transactions. The electronic device displays a first graphical user interface (GUI) on a touch screen, the first GUI including a currency amount, displays a second GUI corresponding to transmission of the currency amount according to a currency transmission signal input to the touch screen, determines an amount of an electronic transaction according to the currency transmission signal, and transmits a generated signal containing information on the amount of the electronic transaction to an information processing system.

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.