Patents by Inventor Wen Liao

Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220093687
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20220093849
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 24, 2022
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20220085280
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 17, 2022
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20220037370
    Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.
    Type: Application
    Filed: June 21, 2021
    Publication date: February 3, 2022
    Applicant: Au Optronics Corporation
    Inventors: Yueh-Chi Wu, Ti-Kuei Yu, Shu-Wen Liao
  • Patent number: 11239279
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11222788
    Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Wen Liao, Jun-Xiu Liu, Chun-Chih Lin
  • Publication number: 20210408373
    Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsia-Wei CHEN, Chih-Hung PAN, Chih-Hsiang CHANG, Yu-Wen LIAO, Wen-Ting CHU
  • Publication number: 20210404008
    Abstract: A microRNA (miRNA) expression signature for predicting triple-negative breast cancer (TNBC) recurrence is provided. The miRNA expression signature consists essentially of hsa-miR-139-5p, hsa-miR-10b-5p, hsa-miR-486-5p, hsa-miR-455-3p, hsa-miR-107, hsa-miR-146b-5p, hsa-miR-324-5p, and hsa-miR-20a-5p.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Kuang-Wen LIAO, Hsien-Da HUANG, Hsiao-Chin HONG, Cheng-Hsun CHUANG
  • Publication number: 20210396619
    Abstract: Described herein are techniques to enable a mobile device to perform multi-source estimation of an altitude for a location. A baseline altitude may be determined at ground level for a location and used to calibrate a barometric pressure sensor on the mobile device. The calibrated barometric pressure sensor can then estimate changes in altitude relative to ground level based on detected pressure differentials, allowing a relative altitude to ground to be determined. Baseline calibration for the barometric sensor calibration can be performed to determine an ambient ground-level barometric pressure.
    Type: Application
    Filed: January 29, 2021
    Publication date: December 23, 2021
    Inventors: Lei Wang, William J. Bencze, Kumar Gaurav Chhokra, Fatemeh Ghafoori, Stephen P. Jackson, Cheng Jia, Yi-Wen Liao, Glenn D. Macgougan, Isaac T. Miller, Alexandru Popovici, Christina Selle, Aditya Narain Srivastava, Richard Warren, Michael P. Dal Santo, Pejman Lotfali Kazemi
  • Publication number: 20210391189
    Abstract: A wet etch apparatus includes a wafer chuck, a dispensing nozzle, a liquid etchant container, and an electric field generator. The dispensing nozzle is above the wafer chuck. The liquid etchant container is in fluid communication with the dispensing nozzle. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator includes a first electrode and a second electrode spaced apart from the first electrode in a direction substantially perpendicular to a top surface of the wafer chuck, and the second electrode is an electrode plate above the wafer chuck.
    Type: Application
    Filed: August 28, 2021
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hong-Ting LU, Han-Wen LIAO
  • Patent number: 11201190
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11201281
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20210384421
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chin-Yu Mei, Po-Hao Tseng
  • Publication number: 20210377142
    Abstract: An equipment detection system includes a processor, a communication module, and a display module. The processor is configured to detect a connection to an external device. The processor enumerates device information about the external device, obtains user information from a local host, and generates a data structure according to the device information and the user information. The processor is included in the local host. The communication module is configured to transmit the data structure and receive status information. The status information includes a placement space corresponding to the external device or the status of the external device. The status information is associated with the data structure. Moreover, the display module is configured to display the status information.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 2, 2021
    Inventors: Fang-Wen LIAO, Ping-Hung CHEN
  • Publication number: 20210366988
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20210321546
    Abstract: A heat dissipating module includes a heat dissipating substrate, a first structural plate, and a first heat conductive plate. The heat dissipating substrate has an inlet, an outlet, and a first container formed on a top surface of the heat dissipating substrate. The inlet and the outlet are communicated with the first container respectively. The first structural plate has a first channel member and is contained in the first container. The first channel member is communicated with the inlet and the outlet respectively. Heat dissipating liquid flows through the first channel member via the inlet, and flows out of the heat dissipating module via the outlet. The first heat conductive plate covers the first structural plate. The first heat conductive plate is in contact with a heat generating member for conducting heat energy generated by the heat generating member to the heat dissipating liquid.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 14, 2021
    Inventor: Tzu-Wen Liao
  • Publication number: 20210296401
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20210284580
    Abstract: Methods, apparatus and systems using heat exchanger reactors to form polymer derived ceramic materials, including methods for making polysilocarb (SiOC) precursors.
    Type: Application
    Filed: November 16, 2020
    Publication date: September 16, 2021
    Applicant: Melior Innovations, Inc.
    Inventors: Richard Landtiser, Wen Liao, Connor Kilgallen, Douglas Dukes, Isabel Burlingham
  • Publication number: 20210280692
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 9, 2021
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Patent number: D944803
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 1, 2022
    Assignee: GUANGDONG GOPOD GROUP CO., LTD.
    Inventor: Zhuo-Wen Liao