Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A portable electronic device is provided and includes a first display module, a second display module, a keyboard device, a sensing unit and a control unit. The second display module is pivotally connected to the first display module. The sensing unit is configured to sense a position of the keyboard device relative to the second display module to output a sensing signal. The control unit is configured to control a displaying image of the second display module according to the sensing signal.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.

Abstract: A network computer system attributes deviation from a predicted travel distance or trip time for arranged transport services. A network computer system monitors a service provider of an arranged transport service to determine a distance traveled, as well as an expended duration. The network computer system compares the determined distance traveled and/or the expended duration with a predicted distance and/or duration of travel to determine if a deviation exists. An adjustment value for the service value may be determined and communicated, based the traveled distance and the expended duration as compared to the predicted distance and/or duration of travel.

Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.

Abstract: A manufacturing method of a composite photovoltaic structure including a step of forming a transparent electrode material, a step of forming a first photovoltaic unit, a step of forming a first insulation layer, a step of forming a first transparent conductive layer, a step of forming a second photovoltaic unit, a step of forming a second insulation layer, a step of forming a second transparent conductive layer and a step of splitting a product. Thus, the manufacturing method of the composite photovoltaic structure has a photoelectric reaction area of a significantly improved omnidirectional concentration gain, an efficiently induced current and a low manufacturing cost, without affecting the whole structure thickness.

Abstract: A composite photovoltaic structure having the following components is illustrated. A first photovoltaic unit is disposed on a transparent substrate, and electrically connected to a second photovoltaic unit in parallel, and the second photovoltaic unit is stacked on the first photovoltaic unit. The first photovoltaic unit is disposed on a second transparent electrode layer, and a first transparent conductive layer is disposed on a top of the first photovoltaic unit and electrically connected to a first transparent electrode layer, and the second photovoltaic unit is disposed on the first transparent conductive layer. A second transparent conductive layer is disposed on the second photovoltaic unit and is electrically connected to the second transparent electrode layer.

Abstract: A cluster tool includes a polyhedral transfer chamber, at least one processing chamber, at least one load lock chamber, and an electron beam (e-beam) source. The processing chamber is connected to the polyhedral transfer chamber. The processing chamber is configured to perform a manufacturing procedure to a wafer present therein. The load lock chamber is connected to the polyhedral transfer chamber. The e-beam source is configured to performing an e-beam treatment to the wafer after the wafer is performed the manufacturing procedure.

Abstract: A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.

Abstract: A liquid-cooled heat dissipation device is disclosed, comprising a main body, a centrifugal pump, an inlet pipe and an outlet pipe. The main body comprises liquid flow channels and liquid storage tanks. The liquid flow channels are circumferentially arranged and spaced apart. The liquid storage tanks are located on both sides of the main body, and the liquid storage tanks on the same side are connected by liquid flow channels. The centrifugal pump is installed in one of the liquid storage tanks. The inlet pipe and the outlet pipe are in spatial communication with the other two liquid storage tanks, respectively. The centrifugal pump guides a cooling liquid through the inlet pipe, main body and outlet pipe. The cooling liquid travel through the liquid storage tanks via the liquid flow channels and forms radial jet flows after being pumped by centrifugal pump.

Abstract: A liquid-cooled heat dissipation device is disclosed, comprising a main body, a centrifugal pump, an inlet pipe, an outlet pipe, a centrifugal fan and a motor. The main body comprises a shaft hole, liquid flow channels and airflow channels. The centrifugal pump guides a cooling liquid through the inlet pipe, main body and outlet pipe. The centrifugal fan guides air into the main body axially from the shaft hole. After passing through the centrifugal fan, the air forms centrifugal airflows and leaves the body radially through the airflow channels. With an extended flow path of the cooling liquid and the radial flow of the centrifugal airflow provided by the present invention, the temperature of the cooling liquid may be quickly reduced and the cooling effect may be improved. Thus, the structure is compact, small, light-weight, easy-to-assemble.

Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

Abstract: A coating apparatus for forming a coating film over a substrate includes a spin chuck for holding and rotating the substrate, a central coating nozzle over a central portion of the substrate, a plurality of first coating nozzles surrounding the central coating nozzle and spaced apart from the central coating nozzle by substantially a same first distance, and a plurality of second coating nozzles surrounding the central coating nozzle and spaced apart from the central coating nozzle by substantially a same second distance, wherein the second distance is greater than the first distance.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.