Abstract: An anti-glare and anti-reflection device including a base and an anti-reflection film is provided. The base includes a plurality of micro protrusions. The micro protrusions are connected to each other to form a rough surface. The rough surface has a first point furthest from a display surface and a second point closest to the display surface. A distance between the first point and the second point in a normal direction of the display surface is HD, and 1 ?m?HD?20 ?m. A normal projection of each of the micro protrusions on the display surface has a first axis length R1 and a second axis length R2, 1 ?m?R1?20 ?m, and 1 ?m?R2?20 ?m. The anti-reflection film is disposed on the rough surface. The anti-reflection film has a thickness T in a normal direction of the rough surface, and T/H?0.1.

Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.

Abstract: The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.

Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.

Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.

Abstract: A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.

Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

Abstract: A photoelectric resonance chip includes, a chip main body, signal receiver having a first coil, encoding device, signal generator having a second coil; and at least one light wave generating element and at least one electric wave generating element. When a user carries the chip main body on their body, the first coil converts the type of external microwave from energy wave to current, the signal receiver receives the signals and transmits them to the encoding device, the encoding device increases the frequencies of the signals by means modulation to enlarge the power thereof and transmits them to the signal generator, the second coil converts the type of the signal from current to energy wave, the signal generator feeds the enlarged microwave back to the user's body, and the microwave fed back to the body carries light wave energy and electric wave energy to flow around the whole body.

Abstract: The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.

Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.

Abstract: An apparatus for removing a photoresist layer from at least one alignment mark of a wafer is provided. The apparatus includes a holder, a solvent dispenser, and a suction unit. The holder is used to support the wafer, wherein the alignment mark is formed in a peripheral region of the wafer. The solvent dispenser is used to spray a solvent onto the photoresist layer on the alignment mark of the wafer to generate a dissolved photoresist layer. The suction unit is used to remove the dissolved photoresist layer and the solvent from the wafer through exhausting.

Abstract: A network computer system attributes deviation from a predicted travel distance or trip time for arranged transport services. A network computer system monitors a service provider of an arranged transport service to determine a distance traveled, as well as an expended duration. The network computer system compares the determined distance traveled and/or the expended duration with a predicted distance and/or duration of travel to determine if a deviation exists. An adjustment value for the service value may be determined and communicated, based the traveled distance and the expended duration as compared to the predicted distance and/or duration of travel.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.