Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.

Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.

Abstract: An electronic device includes a display unit; a memory unit; and a processing unit electrically connected to the display unit and the memory unit, the processing unit capturing (N+M) frames displayed by the display unit, N and M being positive integers, the N frames having a first resolution, the M frames having a second resolution, the first resolution being larger than the second resolution, the processing unit converting a color space of the (N+M) frames and encoding the (N+M) frames, the processing unit magnifying a size of each of the M frames to be equal to a size of each of the N frames, the processing unit encapsulating and outputting the (N+M) frames.

Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.

Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.

Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.

Abstract: One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Abstract: An apparatus includes a body and a surface for receiving a semiconductor wafer carrier is provided. A nozzle and a venting hole are provided on the surface. The semiconductor wafer carrier has at least one selectively closable capped opening at a bottom, top and/or side surface thereof. The capped opening is configured to couple to, and be accessible by, the nozzle and receive gas output from the nozzle so as to create a substantially oxygen free environment within the semiconductor wafer carrier. The vent hole is configured to allow gas to flow out of the semiconductor wafer carrier. In addition, the apparatus includes a sensor and a controller. The sensor is configured to monitor an ambient condition in the semiconductor wafer carrier, and the controller is configured to adjust a control valve based on the ambient condition so as to control the gas flow or output from the nozzle.

Abstract: The present disclosure provides a multi-media extension method. The multi-media extension method includes capturing a multi-media file in a first format from a mobile device when a first wireless link is established between the mobile device and a computer system, converting the multi-media file with the first format to a multi-media file with a second format, compressing the multi-media with the second format into a plurality of data packets, and sending and receiving the data packets via the first wireless link, de-compressing the packets to the multi-media file with the second format, converting the multi-media file with the second format back to the multi-media file with the first format and playing the multi-media file with the first format on the computer system.

Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar with a top surface of the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the source/drain region.

Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.

Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.

Abstract: An easily taken and carried holder for boots is provided with a flexible handle and two holding assemblies secured to both ends of the flexible handle respectively. Each of the holding assemblies comprises an internal space and a magnet in the space. The magnet has two poles so that the magnets of the holding assemblies can attract each other to bring the boots into contact when the holding assembles are inserted into the boots. The flexible handle can be used to take and suspend the boots. The ferromagnetic members can kept the boots upright and prevent the boots from falling to cause wrinkles when the ferromagnetic members are inserted into the boots to be attracted by the magnets. The invention has characteristics of easy taking, secure hold, practicability, and convenient storage.

Abstract: The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.