Abstract: A method of forming a magnetoresistive random access memory (MRAM) device including a perpendicular MTJ (magnetic tunnel junction) is provided. The method includes forming a magnetic tunneling junction (MTJ) over a bottom electrode layer. A top electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the top electrode layer. A first etch is performed through the top electrode layer, through regions of the MTJ unmasked by the hard mask, to form a top electrode and an etched MTJ. Sidewall spacers are formed extending from an upper surface of the hard mask or the top electrode, along sidewalls of the top electrode and the etched MTJ, to a point below or about even with an upper surface of the bottom electrode. A resulting MRAM device structure is also provided.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.

Abstract: An electronic device includes a display unit; a memory unit; and a processing unit electrically connected to the display unit and the memory unit, the processing unit capturing (N+M) frames displayed by the display unit, N and M being positive integers, the N frames having a first resolution, the M frames having a second resolution, the first resolution being larger than the second resolution, the processing unit converting a color space of the (N+M) frames and encoding the (N+M) frames, the processing unit magnifying a size of each of the M frames to be equal to a size of each of the N frames, the processing unit encapsulating and outputting the (N+M) frames.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.

Abstract: One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions.

Abstract: A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.

Abstract: The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.

Abstract: A method of connecting device adapted to an interactive whiteboard system and a host device thereof are provided. The host device has an interactive display device. The method includes the following steps. A scanning process is executed to receive a notification signal which is continuously broadcast by a first client device. A representative icon is obtained from an icon base, and the representative icon is set according to device information of the first client device in the notification signal, such that the representative icon is related to the first client device. The representative icon is displayed on the interactive display device, and then a broadcast termination signal is transmitted back to the first client device after the representative icon is displayed. After receiving the broadcast termination signal, the first client device stops broadcasting the notification signal.

Abstract: A method and system of sharing data and a server apparatus thereof are provided. The method includes following steps. When a first operation command is detected, first operation information is transmitted from a server apparatus to a first client apparatus. The first operation information is received by the first client apparatus to execute a first operation, and data information related to a data object is generated and transmitted to the server apparatus. The data information is received and transmitted to other client apparatuses by the server apparatus, so as to enable a second operation related to the data object. When a second operation command is detected, second operation information is transmitted to a second client apparatus by the server apparatus. In response to the second operation information, the second client apparatus is connected to the first client apparatus to obtain the data object according to the data information.

Abstract: A method for sharing a control right and a host device are provided. The method of sharing the control right is adapted to the host device of an interactive whiteboard system. The method includes the following steps. A scanning process is executed to receive an online notification signal broadcast by a first client device, wherein the online notification signal includes a weight value and device information of the first client device; it is determined whether the control right of the interactive whiteboard system is released or not, and when the control right of the interactive whiteboard system is not released, it is determined whether to share the control right of the interactive whiteboard system to the first client device according to the weight value. When the control right is determined to be shared to the first client device, a control right notification signal is transmitted to the first client device.

Abstract: One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.

Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar with a top surface of the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the source/drain region.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.