Patents by Inventor Wen Liao

Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170141301
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode.
    Type: Application
    Filed: July 29, 2016
    Publication date: May 18, 2017
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Publication number: 20170141305
    Abstract: The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.
    Type: Application
    Filed: September 26, 2016
    Publication date: May 18, 2017
    Inventors: Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9631273
    Abstract: An apparatus comprises a first gas inlet coupled between a first pipe and a reaction chamber, wherein the first pipe configured to carry process gases, a second gas inlet coupled between a second pipe and the reaction chamber, wherein the second pipe configured to carry a precursor material in a gaseous state and a heating device coupled to the second pipe and the second gas inlet, wherein the heating device keeps an ambient temperature of the second pipe and the second gas inlet above a boiling point of the precursor material.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Hai Wang, Ding-I Liu, Si-Wen Liao, Po-Hsiung Leu, Yong-Hung Yang
  • Publication number: 20170107619
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Application
    Filed: July 27, 2016
    Publication date: April 20, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chan LO, Yi-Fang LAI, Po-Hsiung LEU, Ding-I LIU, Si-Wen LIAO, Kai-Shiung HSU, Jheng-Uei HSIEH, Shian-Huei LIN, Jui-Fu HSU, Cheng-Tsung WU
  • Publication number: 20170098764
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9607873
    Abstract: An apparatus includes a body and a surface for receiving a semiconductor wafer carrier is provided. A nozzle and a venting hole are provided on the surface. The semiconductor wafer carrier has at least one selectively closable capped opening at a bottom, top and/or side surface thereof. The capped opening is configured to couple to, and be accessible by, the nozzle and receive gas output from the nozzle so as to create a substantially oxygen free environment within the semiconductor wafer carrier. The vent hole is configured to allow gas to flow out of the semiconductor wafer carrier. In addition, the apparatus includes a sensor and a controller. The sensor is configured to monitor an ambient condition in the semiconductor wafer carrier, and the controller is configured to adjust a control valve based on the ambient condition so as to control the gas flow or output from the nozzle.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Si-Wen Liao, Jia-Wei Xu, Mao-Cheng Lin, Chien-Cheng Wu, Lan-Hai Wang, Ding-I Liu, Fu-Shun Lo
  • Patent number: 9573144
    Abstract: A method of forming a coating film over a substrate is provided. The method includes spinning the substrate. The method further includes providing a central coating liquid spray over a central portion of the substrate. The method also includes providing first coating liquid sprays over the substrate. The first coating liquid sprays surround the central coating liquid spray and are spaced apart from the central coating liquid spray by a same first distance.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lan-Hai Wang, Yong-Hung Yang, Ding-I Liu, Si-Wen Liao, Po-Hsiung Leu, Mao-Cheng Lin
  • Patent number: 9577009
    Abstract: The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20170033159
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9553265
    Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Sheng Yang, Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Yu-Wen Liao, Manish Kumar Singh
  • Patent number: 9543511
    Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Ting Sung, Chang-Ming Wu, Hsia-Wei Chen, Shih-Chang Liu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9537094
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20160380193
    Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Publication number: 20160343625
    Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.
    Type: Application
    Filed: August 26, 2015
    Publication date: November 24, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Tsung WU, Po-Hsiung LEU, Ding-I LIU, Si-Wen LIAO, Hsiang-Sheng KUNG
  • Patent number: 9490152
    Abstract: A production tool includes a chamber, a heater in the chamber, and a pumping outlet on a side of the heater. A pumping liner is in the chamber and encircling the heater. The pumping liner and the heater have a first gap therebetween and a second gap therebetween. The second gap is different from the first gap, and the second gap is farther away from the first pumping outlet than the first gap.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Hai Wang, Ding-I Liu, Si-Wen Liao, Yong-Hung Yang, Jia-Wei Hsu
  • Patent number: 9479716
    Abstract: An image processing method comprises: receiving a first image; setting at least one first region on the first image, where the first image comprises at least one line; calculating a first average value of the first region; performing computation on the first image with a first parameter set to generate a second image; setting a second region of the second image according to the first region, and calculating a second average value of the second region; calculating a difference between the first average value and the second average value; and determining whether to replace the first image with the second image according to the difference.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: October 25, 2016
    Assignee: ABILITY ENTERPRISE CO., LTD.
    Inventors: Tzu-Wen Liao, Yi-Jian Lee
  • Patent number: 9478638
    Abstract: The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen
  • Patent number: 9466794
    Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen, Kuo-Chi Tu, Ching-Pei Hsieh
  • Patent number: 9461245
    Abstract: The present disclosure relates to an RRAM cell having a multi-layer bottom electrode with an insulating core, which provides for good gap fill ability, and an associated method of formation. In some embodiments, the RRAM cell has a multi-layer bottom electrode with an insulating bottom electrode (BE) layer arranged laterally between sidewalls of a conductive lower BE layer and vertically between the conductive lower BE layer and a conductive upper BE layer. A dielectric data storage layer having a variable resistance is arranged over the multi-layer bottom electrode, and a top electrode is arranged over the dielectric data storage layer. The insulating core of the bottom electrode is better able to fill gaps with large aspect ratios than conductive materials, thereby giving the multi-layer bottom electrode a planar upper surface that avoids topography problems in overlying layers.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20160276408
    Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode coplanar with the gate, a resistive material layer over the bottom electrode, a top electrode over the resistive material layer, and a conductive material electrically connecting the bottom electrode to the source/drain region.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Chih-Yang CHANG, Wen-Ting CHU, Kuo-Chi TU, Yu-Wen LIAO, Hsia-Wei CHEN, Chin-Chieh YANG