Patents by Inventor Wen Lin

Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250241028
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, an inner spacer layer sandwiched between the source/drain feature and the gate stack and between the first nanostructure and the second nanostructure, a semiconductor feature at a corner between the inner spacer layer and the first nanostructure, and a first passivation layer sandwiched between a first surface of the semiconductor feature and the gate stack.
    Type: Application
    Filed: March 17, 2025
    Publication date: July 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin LEE, Choh-Fei YEAP, Da-Wen LIN, Chih-Chieh YEH
  • Patent number: 12368613
    Abstract: A method for use in a system including an Ethernet Virtual Private Network (EVPN) core network and a VXLAN data plane, a first gateway device GW1 and a second gateway device GW2 operating in an all-active multihoming mode to interconnect the EVPN core network and VXLAN data plane, is described. The method includes establishing, by the second gateway device GW2, a VXLAN tunnel to a remote VTEP X before traffic is sent by the remote VTEP X and received by the second gateway device GW2, but after traffic is sent by the remote VTEP X and received by the first gateway device GW1. wherein the first and second gateway devices GW1 and GW2 use an anycast IP address as a source address for VTEP X.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: July 22, 2025
    Assignee: Juniper Networks, Inc.
    Inventors: Wen Lin, Vrishabha Sikand, Kranthi Kumar Katam, Selvakumar Sivaraj, Moo Jin Jeong, Jagadish N. Grandhi, Pratibha Goel
  • Patent number: 12363937
    Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.
    Type: Grant
    Filed: June 26, 2024
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Choh Fei Yeap, Da-Wen Lin, Chih-Chieh Yeh
  • Publication number: 20250224938
    Abstract: Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: performing static analysis of program source code defining a computer program, wherein the computer program comprises a pointer operation callee and at least one caller that can pass a pointer parameter to the pointer operation callee; generating, in dependence on the static analysis of program source code, binary code executable so that the pointer operation callee, in runtime, performs a runtime check for determining pointer alias status of the pointer operation callee; and generating, in dependence on the static analysis of program source code, executable binary code executable so that the pointer operation callee, in runtime, performs selecting and activating an executable code path in dependence on a result of the runtime check.
    Type: Application
    Filed: January 9, 2024
    Publication date: July 10, 2025
    Inventors: Zheng CHEN, Ke Wen LIN, Jiu Fu GUO, Kai LUO
  • Publication number: 20250219947
    Abstract: A controller device receives, from a plurality of assisted replication network devices, respective utilization information associated with the plurality of assisted replication network devices. The controller device generates, based on the respective utilization information associated with the plurality of assisted replication network devices, load balancing information for a network device associated with two or more assisted replication network devices of the plurality of assisted replication network devices, and sends, to the network device, the load balancing information. The network selects, based on the load balancing information, a particular assisted replication network device of the two or more assisted replication network devices.
    Type: Application
    Filed: March 18, 2025
    Publication date: July 3, 2025
    Inventors: Vikram NAGARAJAN, Wen LIN, Soumyodeep JOARDER, Muniyappan SURUTTAIYAN, Princy T. ELIZABETH, Ragupathi J, SelvaKumar SIVARAJ
  • Patent number: 12345911
    Abstract: An embodiment of the invention provides a display module including a plurality of light sources, a light guide plate, a reflective element, a reflective display unit, and a reflective polarizer. The light sources are configured to provide a plurality of illumination beams. The light guide plate has a first surface, a second surface, and a plurality of incident surfaces. The illumination beams enter the light guide plate through the incident surfaces. The reflective element is configured to change a propagation direction of at least one part of the illumination beams. The reflective element includes a plurality of reflective surfaces, and the reflective surfaces reflect the illumination beams having a first polarization direction. The reflective display unit is capable of modulating a polarization state of the illumination beams to form modulated beams. The reflective polarizer filters the modulated beams into an image beam.
    Type: Grant
    Filed: September 2, 2024
    Date of Patent: July 1, 2025
    Assignee: Himax Display, Inc.
    Inventors: Yuet-Wing Li, Kuan-Yu Chen, Chi-Wen Lin
  • Patent number: 12341106
    Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Lin, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
  • Patent number: 12339572
    Abstract: A heat dissipating module includes a casing including a bottom plate and a water inlet; a cover plate disposed on one side of the casing opposite to the bottom plate; a pressurizing device moving back and forth in the casing and having a maximum stroke; a water pump disposed between the bottom plate and the pressurizing device, where liquid fills a space between the water pump and the pressurizing device to define a water tank; and a stop valve disposed in the water tank and located between the pressurizing device and the water pump. According to a direction from the bottom plate to the cover plate, the height of the water inlet is lower than the stop valve. The heat dissipating module has a small volume and is configured to flip at multiple angles. A projection device including the heat dissipating module and having structural reliability is also provided.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: June 24, 2025
    Assignee: Coretronic Corporation
    Inventors: Shi-Wen Lin, Wei-Chi Liu, Tsung-Ching Lin
  • Publication number: 20250189838
    Abstract: A display panel includes a first substrate, a second substrate, a sealant configured to mount the first substrate and the second substrate at a frame area; a display array disposed at a display area of the first substrate and the second substrate, in which the display area is surrounded by the frame area, a planarization layer disposed on an outer surface of the first substrate and including a plurality of reflective cavities, and a micro-LED array disposed at the frame area and including a plurality of micro-LEDs. The micro-LEDs are disposed in the reflective cavities.
    Type: Application
    Filed: November 14, 2024
    Publication date: June 12, 2025
    Inventors: Shang-Wei HSIEH, Jia-Hong Wang, Yi-Wen Lin, Wang-Shuo Kao, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20250189876
    Abstract: A thermal module including a heat sink and a projector are provided. The heat sink includes a body and heat sink fins. The body includes a fixed plate and partition plates. The fixed plate has a first surface, a second surface and a third surface. The first surface is opposite to the second surface, and the third surface is connected to the first and second surfaces. Spaces form between the partition plates, and the heat sink fin is disposed correspondingly in each space. Each heat sink fin has a corrugated structure with multiple segments, and a fractured structure is provided on the surface of each segment. The third surface and the side surface connected to the end surfaces of the partition plates form an air guide surface, and the heat sink receives or discharges air flow with the air guide surface.
    Type: Application
    Filed: November 20, 2024
    Publication date: June 12, 2025
    Applicant: Coretronic Corporation
    Inventors: Pei-Rong Wu, Shi-Wen Lin
  • Patent number: 12323317
    Abstract: A network device may originate a route, and may designate the route as a first colored route having a first color. The network device may advertise the first colored route to a first intermediate network device to cause the first intermediate network device to propagate the first colored route to an ingress network device over a first colored border gateway protocol session. The network device may designate the route as a second colored route having a second color, and may advertise the second colored route to a second intermediate network device to cause the second intermediate network device to propagate the second colored route to the ingress network device over a second colored border gateway protocol session.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: June 3, 2025
    Assignee: Juniper Networks, Inc.
    Inventors: Kevin Wang, Michal Styszynski, Wen Lin
  • Patent number: 12324190
    Abstract: The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: June 3, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min Jiao, Ji-Yin Tsai, Da-Wen Lin, Hung-Ju Chou
  • Patent number: 12317864
    Abstract: A body-worn structure includes a support enclosure provided with a front harness, the front harness is provided with a first traverse belt and a second transverse belt, the first traverse belt is connected with the second traverse belt. Two ends of the first traverse belt are respectively fitted with left and right female buckles. Two ends of the second traverse belt are respectively fitted with a second traverse belt male buckle and a corresponding second traverse belt female buckle to facilitate clasping each other together; either side of the second traverse belt male buckle or the second traverse belt female buckle is provided with at least a fixing ring; the second traverse belt female buckle is replaceable alternatively by the second traverse belt male buckle and vise versa.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: June 3, 2025
    Inventor: Che-Wen Lin
  • Patent number: 12323327
    Abstract: Techniques for EVPN Host Routed Bridging (HRB) and EVPN cloud-native data center with Host Routed Bridging (HRB) are described. A host computing device of a data center includes one or more containerized user-level applications. A cloud native virtual router is configured for dynamic deployment by the data center application orchestration engine and operable in a user space of the host computing device. Processing circuitry is configured for execution of the containerized user-level applications and the cloud native virtual router. The cloud native virtual router comprises a containerized routing protocol process configured to operate as a control plane, and a data plane for the containerized router. The data plane is configured to operate an ethernet virtual private network (EVPN) encapsulation/decapsulation data path of an overlay network for communicating layer two (L2) network traffic of the containerized user applications over a switch fabric of the data center.
    Type: Grant
    Filed: December 13, 2023
    Date of Patent: June 3, 2025
    Assignee: Juniper Networks, Inc.
    Inventors: Wen Lin, Manish Gupta, Shivakumar Channalli, Vinay K Nallamothu
  • Publication number: 20250172861
    Abstract: A heat dissipation module configured to dissipate heat from a rotating element rotated with a first axis as a rotation axis is provided. The heat dissipation module includes at least one first fan and a heat dissipation component. The at least one first fan includes a first fan outlet. A first airflow generated by the at least one first fan flows from the first fan outlet to the rotating element. The heat dissipation component includes an inlet duct, a plurality of inner ducts and at least one outlet duct. The plurality of inner ducts are communicated to the inlet duct and the at least one outlet duct. The inlet duct of the heat dissipation component is disposed corresponding to a rotation tangential direction of the rotating element, and the rotation tangential direction is perpendicular to the first axis. In addition, a projection device is also mentioned.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 29, 2025
    Applicant: Coretronic Corporation
    Inventors: Pei-Rong Wu, Shi-Wen Lin
  • Patent number: 12317578
    Abstract: Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Yuan Wu, Ka-Hing Fung, Min Jiao, Da-Wen Lin, Wei-Yuan Jheng
  • Publication number: 20250156618
    Abstract: A method for designing an integrated circuit comprises identifying a first circuit component that presents a voltage (IR) drop being equal to or greater than an IR drop threshold through at least an IR drop analysis, splitting the plurality of timing paths into a first subset of timing paths and a second subset of timing paths, based on a timing margin threshold; and adding a second circuit component disposed along the second subset of timing paths, while keeping the first circuit component disposed along the first subset of timing paths. The first circuit component can be disposed along a plurality of timing paths that each extend from a first storage node and to a second storage node and can be each associated with a timing margin.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 15, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Lin, Wei-Chih Hsieh, Florentin Dartu
  • Patent number: 12292674
    Abstract: A heat dissipation module, configured for heat dissipation of at least one first heat source and at least one second heat source, and including a first heat sink, a second heat sink, a first pipe, and a second pipe, is provided. The first heat sink and the first heat source are connected to each other through the first pipe to form a first loop, so that a liquid medium flows through the first heat sink for heat exchange and then flows to the first heat source for circulating heat dissipation. The second heat sink and the second heat source are connected to each other through the second pipe to form a second loop, so that the liquid medium flows through the second heat sink for heat exchange and then flows to the second heat source for circulating heat dissipation. A projection device, including the heat dissipation module, is also provided.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 6, 2025
    Assignee: Coretronic Corporation
    Inventors: Pei-Rong Wu, Shi-Wen Lin
  • Publication number: 20250140392
    Abstract: A method for retrieving information about similar medical devices is provided, which includes the following steps: obtaining a first technical context of a specific medical device; utilizing a first machine-learning model to extract one or more technical items of the specific medical device based on technical content of the first technical context; utilizing the first machine-learning model to generate candidate medical devices using the technical items; searching a database for device information about the candidate medical devices; retrieving summary files of the candidate medical devices from the database based on the device information; utilizing the first machine-learning model to infer a second technical context of each candidate medical device; and determining a most similar medical device for the specific medical device according to a similarity score for each candidate medical device calculated from the second technical context and the first technical context using a second machine-learning model.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventors: BOU-WEN LIN, KUAN-JU WANG, CHIH-YU AN
  • Publication number: 20250133927
    Abstract: An electronic device includes a flexible substrate and a conductive wire structure. The conductive wire structure is disposed on the flexible substrate and includes a first segment, a second segment, a third segment, a fourth segment, a first joint portion, a second joint portion, a third joint portion and a fourth joint portion. A first opening is surrounded by the first segment, the second segment, the first joint portion and the second joint portion. A second opening is surrounded by the third segment, the fourth segment, the third joint portion and the fourth joint portion. Along a first direction, a ratio of a first width sum of widths of the first segment, the second segment, the third segment and the fourth segment to a second width sum of widths of the first joint portion and the third joint portion is in a range from 0.8 to 1.2.
    Type: Application
    Filed: January 2, 2025
    Publication date: April 24, 2025
    Applicant: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang