Patents by Inventor Wen Lin

Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097330
    Abstract: An antenna system includes a first antenna element and a second antenna element. The first antenna element includes a first ground element, a first radiation element, a second radiation element, and a third radiation element. The first radiation element has a first feeding point. The second radiation element is coupled to the first ground element. The third radiation element is coupled to the first ground element. The third radiation element is adjacent to the first radiation element and the second radiation element. The second antenna element includes a second ground element, a fourth radiation element, a fifth radiation element, and a sixth radiation element. The fourth radiation element has a second feeding point. The fifth radiation element is adjacent to the fourth radiation element. The fifth radiation element is coupled through the sixth radiation element to the second ground element.
    Type: Application
    Filed: October 31, 2022
    Publication date: March 21, 2024
    Inventors: Wen Yuan LO, Hui LIN
  • Publication number: 20240092409
    Abstract: In an aspect, a carriage for guided autonomous locomotion may include a computing device configured to produce a safety perimeter, wherein producing further comprises receiving at least an environmental input as a function of an environmental sensor, and producing the safety perimeter as a function of the environmental input, outline at least a corrective action as a function of the safety perimeter, wherein outlining further comprises determining a required force, and outlining the at least a corrective action as a function of the safety perimeter and required force using a corrective machine-learning model, and initiate the at least a corrective action.
    Type: Application
    Filed: October 30, 2023
    Publication date: March 21, 2024
    Applicant: GlüxKind Technologies Inc.
    Inventors: Anne Hunger, Zi Wen Huang, Check Hay Janson Chan, Anderson Jia Lin Kwan
  • Publication number: 20240094783
    Abstract: An example computing device includes a first housing portion, a second housing portion moveably connected to the first housing portion, a link to selectively secure the second housing portion to the first housing portion to inhibit movement of the second housing portion relative to the first housing portion, and a shape-memory alloy element to release the link to allow the second housing portion to move relative to the first housing portion.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Yu-Wen LIN, Chia-Ming TSAI, Shih-Jen CHOU, John Joseph GRODEN
  • Publication number: 20240098026
    Abstract: A controller device receives, from a plurality of assisted replication network devices, respective utilization information associated with the plurality of assisted replication network devices. The controller device generates, based on the respective utilization information associated with the plurality of assisted replication network devices, load balancing information for a network device associated with two or more assisted replication network devices of the plurality of assisted replication network devices, and sends, to the network device, the load balancing information. The network selects, based on the load balancing information, a particular assisted replication network device of the two or more assisted replication network devices.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Vikram NAGARAJAN, Wen LIN, Soumyodeep JOARDER, Muniyappan SURUTTAIYAN, Princy T. ELIZABETH, Ragupathi J, SelvaKumar SIVARAJ
  • Publication number: 20240097038
    Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: October 13, 2022
    Publication date: March 21, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Yi Chuen Eng, Tzu-Feng Chang, Teng-Chuan Hu, Yi-Wen Chen, Yu-Hsiang Lin
  • Publication number: 20240097007
    Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ya-Yi Tsai, Shu-Uei Jang, Chih-Han Lin, Shu-Yuan Ku
  • Publication number: 20240096805
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11935795
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
  • Publication number: 20240088223
    Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Wen SHEN, Yen-Po Lin, Chun-Han Chen
  • Publication number: 20240088141
    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Publication number: 20240090216
    Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han LIN, Chih-Ren HSIEH, Ching-Wen CHAN
  • Publication number: 20240082205
    Abstract: The present invention relates to the use of compounds of formula (I) and formula (II) and/or pharmaceutically acceptable salts of the aforementioned compounds in the treatment of meningioma and the reduction of the recurrence rate of meningioma. In formulas (I) and (II), R1 is C1-C20 alkyl, C3-C10 cycloalkyl, C6-C20 aryl, C1-C20 alkoxy, C6-C20 aryloxy, or halogen; p is 0 to 3; R2 is H, C1-C20 alkyl, or C6-C20 aryl; and R3 is H, C1-C20 alkyl, C3-C10 cycloalkyl, or C6-C20 aryl.
    Type: Application
    Filed: December 29, 2021
    Publication date: March 14, 2024
    Applicant: EVERFRONT BIOTECH INC.
    Inventors: Shinn-Zong LIN, Tsung-Lang CHIU, Horng-Jyh HARN, Tzyy-Wen CHIOU, Jui-Hao LEE
  • Publication number: 20240080268
    Abstract: In some cases, once Fast Reroute (FRR) has taken place (e.g., for MPLS protection), a further FRR is undesirable, and even detrimental. A mechanism to prevent a further FRR, once such a further FRR is determined to be potentially harmful, is described.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Inventors: Kireeti Kompella, Wen Lin, Kevin Wang
  • Publication number: 20240077479
    Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 7, 2024
    Applicant: DeepBrain Tech. Inc
    Inventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
  • Patent number: 11918329
    Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chiung-Wen Lin, Wei-Ru Han, Yang-Ming Chou, Cheng-Nan Tsai, Ren-Hau Gu, Chih-Yuan Chuang
  • Patent number: 11923440
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Patent number: 11920157
    Abstract: Applications of butylidenephthalide (BP), comprising the use of BP in providing a kit for promoting differentiation of stem cells into brown adipose cells, and the use of BP in preparing a medicament, wherein the medicament is used for inhibiting the accumulation of white adipose cells, promoting the conversion of white adipose cells into brown adipose cells, inhibiting weight gain and/or reducing the content of triglycerides, glucose, and total cholesterol in blood.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 5, 2024
    Assignee: NATIONAL DONG HWA UNIVERSITY
    Inventors: Tzyy-Wen Chiou, Shinn-Zong Lin, Horng-Jyh Harn, Hong-Lin Su, Shih-Ping Liu, Kang-Yun Lu, Jeanne Hsieh
  • Patent number: 11920610
    Abstract: An air pump assembly for an inflatable product may include a housing, a cover coupled to the housing, and a rotatable assembly supported by the housing. The rotatable assembly may include a pump housing having first and second air vents, an impeller positioned within the pump housing, a motor operatively coupled to the impeller, and a rotary disc positioned between the pump housing and a vent hole of the housing. The rotatable assembly may be rotatable to a first position wherein air flows from the first air vent of the pump housing to the second air vent of the pump housing and through the vent hole in the housing into an interior of the inflatable product and a second position wherein air flows from the interior of the inflatable product through the vent hole in the housing into the first air vent and then to the second air vent.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Intex Marketing Ltd.
    Inventors: Zhi Xiong Huang, Ying Biao Zhang, Zheng Wen Lin
  • Patent number: 11923367
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Mrunal A Khaderbad, Ziwei Fang, Keng-Chu Lin, Hsueh Wen Tsau