Abstract: An example computing device includes a flexible display coupled to a housing that includes a support plate having a first joint coupled to a first end of the support plate and a second joint coupled to a second end of the support plate. A slide module has a slot that guides a linear slide movement of the second joint along a linear path of movement within the slot as the support plate pivots about the first joint, where the support plate moves according to the first joint and the second joint to support at least the portion of the flexible display when the flexible display is unfolded and moves according to the first joint and the second joint to create a gap between at least a portion of the support plate and at least the portion of the flexible display when the flexible display is folded.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: A method for switching control commands across platforms and a smart device are provided. The smart device, such as a smart screen, connects with a data source by a communication circuitry, displays content received from the data source by a display screen, and includes an input circuitry that provides an input interface circuitry for allowing a control device to connect with the smart device. When an operating system of the smart device receives a command for launching a menu interface from the control device, the menu interface that provides an option of at least one data source is activated. When the data source is selected, the content received from the data source is displayed on the display screen. In the meantime, a signal channel is established between the smart device and the data source in order to forward commands generated by the control device to the data source.

Abstract: A vehicle display device includes a light source module, a light splitting element, first and second polarization reflection modules. The light source module provides a first light beam having a first polarization state and a second light beam having a second polarization state. The light splitting element reflects the first light beam and allows the second light beam to pass through. The first polarization reflection module reflects the first light beam to the light splitting element and converts the first polarization state into the second polarization state. The second polarization reflection module reflects the first and second light beam and convert the second polarization states into third polarization states. The first and second light beam from the second polarization reflection module form a far-field virtual image and a near-field virtual image through the imaging element.

Abstract: A semiconductor device includes semiconductor nanostructures disposed over a substrate, and an electrical isolation region comprising a void disposed over the substrate in a drain/source region. The semiconductor device further includes a source/drain epitaxial layer in contact with the semiconductor nanostructures and disposed over the electrical isolation region in the drain/source region. The source/drain epitaxial layer is disposed over the void. The semiconductor device further includes a gate dielectric layer disposed on and wrapped around each channel region of the semiconductor nanostructures, and a gate electrode layer disposed on the gate dielectric layer and wrapped around each channel region of the semiconductor nanostructures.

Abstract: A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. An electrical insulating and thermal conductive layer is formed over a semiconductor substrate. A dielectric structure is formed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. An opening is formed in the dielectric structure, wherein the opening extending through the dielectric structure and the electrical insulating and thermal conductive layer. A circuit layer is formed in the dielectric structure, wherein the circuit layer fills the opening.

Abstract: Techniques are described for providing fast reroute for BUM traffic in EVPN. For example, a first provider edge (PE) device, elected as a designated forwarder (DF) of an Ethernet segment, configures a backup path using a label received from a second PE device of the Ethernet segment (e.g., backup DF) that identifies the second PE device as a “protector” of the Ethernet segment. For example, a routing component of the DF configures within a forwarding component a backup path to the second PE device, e.g., installing the label and operation(s) within the forwarding component to cause the forwarding component to add the label to BUM packets received from a core network. Therefore, when an access link to the local CE device has failed, the DF reroutes BUM packets from the core network via the backup path to the second PE device, which sends the BUM packets to the CE device.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A foldable device may include a foldable layer and a hinge mechanism. The hinge mechanism may include at least one synchronizing module, at least one torsion module, and a cover module. The at least one synchronizing module may include a synchronizing gear assembly including a first linking gear in meshed engagement with a first rotating link, a second linking gear in meshed engagement with a second rotating link, and at least one intermediate gear in meshed engagement with the first linking gear and the second linking gear. The first rotating link may be coupled to a first housing of a computing device and the second rotating link may be coupled to a second housing of the computing device. The meshed engagement of the first and second rotating links may provide of synchronized, symmetric movement of the first and second housings about a central axis of the computing device.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

Abstract: The present disclosure relates to an anti-fatigue Lactobacillus composition. The anti-fatigue Lactobacillus composition, which includes at least one of Lactobacillus brevis GKEX, Lactobacillus plantarum GKK1 and Lactobacillus johnsonii GKJ2 as an active ingredient, administered to a healthy subject for a continuous period of time, can significantly improve fatigue-related biochemical indices and prolong aerobic exercise time to exhaustion, and thus can be used as an active ingredient for preparation of various compositions for anti-fatigue and/or improving athletic ability.

Abstract: An aquatic liposome encapsulating a natural compound is provided, wherein an average particle size (a median particle size) of the aquatic liposome encapsulating the natural compound ranges from 80 nm to 200 nm. A manufacturing method of an aquatic liposome encapsulating a natural compound is provided and includes performing an ultrasonic oscillation after mixing the aquatic liposome and the natural compound, so that the natural compound is encapsulated in the aquatic liposome. Experiments are conducted to prove that the aquatic liposome encapsulating the natural compound could effectively enter microglia and retinal pigment epithelium cells to relieve the inflammatory response and hinder the apoptosis.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Abstract: A light source module includes a light-emitting device, a light guide pipe, a wave plate, and a polarizer. The light-emitting device emits a beam. The light guide pipe includes a recessed curved surface, an output surface, a first convex surface, and a second convex surface. The recessed curved surface faces the light-emitting device. The output surface is opposite to the recessed curved surface. The first convex surface connects the recessed curved surface with the output surface. The second convex surface connects the recessed curved surface with the output surface and is opposite to the first convex surface, wherein the beam enters the light guide pipe through the recessed curved surface, and leaves the light guide pipe through the output surface. The wave plate is disposed on a path of the beam from the output surface. The polarizer is disposed on a path of the beam from the wave plate.

Abstract: An electronic device includes: a circuit substrate; a first substrate overlapped with the circuit substrate; a first electronic unit attached on the first substrate; a second substrate disposed between the first substrate and the circuit substrate; a first transistor attached on the second substrate and electrically connected to the first electronic unit; and a first conductive element penetrating the second substrate, wherein the first transistor is electrically connected to the circuit substrate through the first conductive element.

Abstract: A method for manufacturing a play-of-color article includes the steps of: (a) providing a first mixture that contains a solvent and a plurality of functionalized colloidal particles; (b) replacing the solvent of the first mixture with a polymer solution that contains polymers, thereby obtaining a second mixture; (c) adding an initiator to the second mixture to obtain a third mixture, followed by injecting the third mixture into a mold and disturbing the third mixture, so that the third mixture is formed with a pattern; (d) leaving the third mixture to stand, so as to allow the functionalized colloidal particles therein to self-assemble to form a crystalline arrangement, thereby obtaining a fourth mixture; and (e) subjecting the polymers in the fourth mixture to a cross-linking reaction, thereby obtaining the play-of-color article. A play-of-color article manufactured by the method, and a play-of-color product including the play-of-color article are also provided.

Abstract: Thermal dissipation and grounding of integrated circuit (IC) devices with backside power delivery networks are discussed. An IC device layer between frontside and backside interconnect sections, composed mostly of an insulating material, is coupled to a crystalline heat spreader or a metal thermal ground layer by an array of thermal pillars extending through the insulating material. The crystalline heat spreader layer may include one or more thermal sensors, such as thermal sensing diodes, also coupled to the IC device layer by one or more thermal pillars. The IC device layer and crystalline layers are coupled by a hybrid bond, which forms the thermal pillars through a continuous section of the insulating material.