Abstract: The present application provides an optical network method and associated apparatus. The method includes: receiving uplink burst time assignment information; and enabling or disabling a laser module of a local end according to the uplink burst time assignment information.

Abstract: A crank apparatus equipped with a labor-saving mechanism and a bicycle crank assembly are disclosed. The crank apparatus includes a crank mechanism, a transmission mechanism, a supporting module and a rotating arm module. The crank mechanism includes a crank, an axle-end gear and a pedal-end gear. The transmission mechanism includes a rotating axle having a circular groove. The supporting module is adapted to sheathe the rotating axle and includes an outer ring and rollers received inside the circular grooves and clamped between the rotating axle and the outer ring. The rotating arm module includes a first rotating arm and a second rotating arm. One end of the second rotating arm is connected to the first rotating arm, and another end of the second rotating arm is connected to the pedal-end gear. Accordingly, the transmission stability and useful lifetime of the crank apparatus and bicycle crank assembly are increased.

Abstract: A computer-implemented method, system and computer program product for reducing register pressure. Loops of a computer program with a number of live variables that exceeds a threshold number, such as the number of available registers with capacity to store data, are identified. Such identified loops may be the to be subject to high register pressure. Upon identifying such loops in the computer program, chains within each identified loop are identified, where each chain includes load and store instructions from the same induction address and where the variable offsets of the load and store instructions are loop invariants. The address expressions for the load and store instructions in the identified chains may then be modified or changed to reuse common variable offsets using an analysis and transformation process. By reusing common variable offsets, there are less variable offsets that need to be stored in the registers thereby mitigating register pressure.

Abstract: The present invention discloses a data access interface unit comprising: a physical storage device controller for receiving a first control signal from a first storage virtualization controller, and accordingly determining the first storage virtualization controller as the primary controller, and generating a first selection signal; a selector for receiving the first selection signal, and accordingly selecting data and signals from the first storage virtualization controller; and a clock generation circuit for providing a dedicated clock signal to the physical storage device, where when the physical storage device controller receives a re-set signal from a second storage virtualization controller, the physical storage device controller determines the second storage virtualization controller as the new primary controller, and accordingly generates a second selection signal so as to control the selector to select data and signals from the second storage virtualization controller.

Abstract: In a method of manufacturing a semiconductor device a semiconductor wafer is retrieved from a load port. The semiconductor wafer is transferred to a treatment device. In the treatment device, the surface of the semiconductor wafer is exposed to a directional stream of plasma wind to clean a particle from the surface of the semiconductor wafer. The stream of plasma wind is generated by an ambient plasma generator and is directed at an oblique angle with respect to a perpendicular plane to the surface of the semiconductor wafer for a predetermined plasma exposure time. After the cleaning, a photo resist layer is disposed on the semiconductor wafer.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A projection device including a casing, an illumination system, a light valve, a first casing member, a second casing member and a projection lens. A color wheel module of the illumination system includes a fixing base, an optical assembly, a first connecting assembly and a second connecting assembly. A driving assembly of the optical assembly is connected to a center of a disk of the optical assembly. On a reference plane perpendicular to the central axis, an orthogonal projection of the first connecting portion and an orthogonal projection of the second connecting portion are respectively located on two sides of the central axis, wherein the first connecting portion of the fixing base is connected to the first casing member through the first connecting assembly, and the second connecting portion is connected to the second casing member through the second connecting assembly.

Abstract: A photolithographic apparatus includes a particle removing cassette, a pump and a compressor. The particle removing cassette includes a first slit that includes an array of parallel wind blade nozzles arranged along a length of the first slit, protruding from the first slit, and configured to eject and direct pressurized cleaning material to a patterning surface of a mask to remove debris particles on the patterning surface. The pump and the compressor are controlled by a controller to adjust a flow rate and a pressure of the pressurized cleaning material based on an amount of debris particles on the patterning surface of the mask.

Abstract: An electronic device is provided on a transport device, including a fastener, an electronic unit, and a first air bag. The electronic unit includes an upper surface and a lower surface opposite to the upper surface. The upper surface is connected to the fastener. The fastener and the first air bag are respectively connected to two opposite sides of the electronic unit. When the first air bag is inflated and expanded, the first air bag covers the lower surface of the electronic unit.

Abstract: An electronic device is disposed on a vehicle body. The electronic device includes a display, a modulation unit and a control unit. The display is connected to the vehicle body through the modulation unit. The control unit is electrically connected to the modulation unit. The control unit controls the modulation unit to regulate a fixed state of the display.

Abstract: A plurality of switches may be arranged according to a spine and leaf topology in which each spine switch is connected to all leaf switches. A leaf switch includes a memory configured to store a plurality of policies, each of the plurality of policies being associated with a respective source identifier value and a respective destination address; a network interface communicatively coupled to one of the spine switches; and a processor implemented in circuitry and configured to: receive a packet from the spine switch via the network interface, the packet being encapsulated with a Virtual Extensible Local Area Network (VXLAN) header; extract a source identifier value from the VXLAN header; determine a destination address for the packet; determine a policy of the plurality of policies to apply to the packet according to the source identifier value and the destination address; and apply the policy to the packet.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A method of forming an electronic device including: providing an assembly, wherein the assembly includes a substrate, an optical film, a plurality of color filters and a defect, wherein the plurality of color filters and the defect are disposed between the substrate and the optical film; and using a laser pulse to form a first processed area that corresponds to the defect in the optical film, wherein the first processed area at least partially overlaps at least two of the plurality of color filters.

Abstract: A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

Abstract: This disclosure relates to a superlattice structure, an LED epitaxial structure, a display device, and a method for manufacturing the LED epitaxial structure. The superlattice structure includes at least two superlattice units which are grown in stacking layers. Each of the at least two superlattice units includes a first n-type GaN layer, a second n-type GaN layer, a first n-type GaInN layer, and a second n-type GaInN layer which are grown in stacking layers. The first n-type GaN layer has a doping concentration which is constant along a growth direction, the second n-type GaN layer has a doping concentration which gradually increases along the growth direction, the first n-type GaInN layer has a doping concentration which gradually decreases along the growth direction, and the second n-type GaInN layer has a doping concentration which is constant along the growth direction.

Abstract: A system comprising an electronic system comprising a plurality of solid state radio frequency (RF) amplifiers and an antenna structure. The antenna structure includes a dielectric substrate and a plurality of antenna elements extending along the dielectric substrate. The antenna structure further includes a plurality of feedlines each of which is coupled to an individual antenna element of the plurality of antenna elements. An output of each of the plurality of solid state RF amplifiers is coupled an individual feedline of the plurality of feedlines.

Abstract: A reordering method performed by a receiving apparatus is provided. The receiving apparatus may receive a first PPDU from a transmitting apparatus, wherein the first PPDU includes a plurality of MPDUs, and the MPDUs correspond to the same BA window. The receiving apparatus may determine a traffic that each of the MPDUs belongs to according to an MPDU identification, wherein traffics that the plurality of MPDUs belonging to include a first traffic and a second traffic which is different from the first traffic. The receiving apparatus may perform a reordering operation for the MPDUs belonging to the first traffic, and a reordering operation for the MPDUs belonging to the second traffic, respectively. The receiving apparatus may transmit a BA frame in response to the first PPDU to the transmitting apparatus, wherein the BA frame includes information for indicating whether the MPDUs in the first PPDU have been successfully received.

Abstract: A computer-implemented method, system and computer program product for reducing register pressure. Loops of a computer program with a number of live variables that exceeds a threshold number, such as the number of available registers with capacity to store data, are identified. Such identified loops may be the to be subject to high register pressure. Upon identifying such loops in the computer program, chains within each identified loop are identified, where each chain includes load and store instructions from the same induction address and where the variable offsets of the load and store instructions are loop invariants. The address expressions for the load and store instructions in the identified chains may then be modified or changed to reuse common variable offsets using an analysis and transformation process. By reusing common variable offsets, there are less variable offsets that need to be stored in the registers thereby mitigating register pressure.

Abstract: An electronic device includes: a circuit board; a plurality of diodes disposed on a first surface of the circuit board; a plurality of first driving circuits disposed on the first surface of the circuit board and electrically connected to the plurality of diodes; and a plurality of second driving circuits electrically connected to the plurality of first driving circuits, wherein a part of the plurality of second driving circuits are disposed on a first substrate, and another part of the second driving circuits are disposed on a second substrate.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.