Patents by Inventor Wen Lin

Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11902160
    Abstract: Techniques for EVPN Host Routed Bridging (HRB) and EVPN cloud-native data center with Host Routed Bridging (HRB) are described. A host computing device of a data center includes one or more containerized user-level applications. A cloud native virtual router is configured for dynamic deployment by the data center application orchestration engine and operable in a user space of the host computing device. Processing circuitry is configured for execution of the containerized user-level applications and the cloud native virtual router. The cloud native virtual router comprises a containerized routing protocol process configured to operate as a control plane, and a data plane for the containerized router. The data plane is configured to operate an ethernet virtual private network (EVPN) encapsulation/decapsulation data path of an overlay network for communicating layer two (L2) network traffic of the containerized user applications over a switch fabric of the data center.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 13, 2024
    Assignee: Juniper Networks, Inc.
    Inventors: Wen Lin, Manish Gupta, Shivakumar Channalli, Vinay K Nallamothu
  • Patent number: 11894443
    Abstract: A method of making a semiconductor device includes depositing a TiN layer over a substrate. The method further includes doping a first portion of the TiN layer using an oxygen-containing plasma treatment. The method further includes doping a second portion of the TiN layer using a nitrogen-containing plasma treatment, wherein the second portion of the TiN layer directly contacts the first portion of the TiN layer. The method further includes forming a first metal gate electrode over the first portion of the TiN layer. The method further includes forming a second metal gate electrode over the second portion of the TiN layer, wherein the first metal gate electrode has a different work function from the second metal gate electrode, and the second metal gate electrode directly contacts the first metal gate electrode.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Patent number: 11890522
    Abstract: An adjustable attachment structure for a swimming machine is disclosed. The attachment structure is configured to interact with a frame of a pool. A user may interact with a locking switch to transition the attachment structure between a locked and an unlocked state. In the unlocked state, the swimming machine may be rotated about an axis to direct a generated current in a number of directions.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: February 6, 2024
    Assignee: Intex Marketing Ltd.
    Inventors: Zhi Xiong Huang, Ying Biao Zhang, Zheng Wen Lin
  • Publication number: 20240031360
    Abstract: According to embodiments of the present invention, method and system for log-in and authorization are disclosed. The system comprises a user device, a server and a mobile device. The user device issues a log-in request. The server receives the log-in request through communication with the user device via a first communication link, and outputs a digital token as one time passwords (OTPs) to the user device in response to the log-in request, for display thereon. The mobile device comprises a communication unit, a camera and a processor. The communication unit communicates with the server via a second communication link. The processor is configured to capture the digital token through the camera, transmit the captured digital token to the server for verification, authenticate a biometric characteristic, and output a notice indicating successful biometric authentication to the server to confirm authorization of the user device. Then, the user device can be used to proceed with an operation with a user account.
    Type: Application
    Filed: March 17, 2023
    Publication date: January 25, 2024
    Applicant: DBS BANK (TAIWAN) LTD.
    Inventors: Chia-Hua WU, Chun-Chin PENG, Shih-Chieh CHUEH, Kuan-Wen LIN
  • Publication number: 20240019486
    Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of package components over a carrier, forming an interconnect structure over and electrically interconnecting the plurality of package components, forming top electrical connectors over and electrically connecting to the interconnect structure, and forming alignment marks at a same level as the top electrical connectors. Probe pads in the top electrical connectors are probed, and the probing is performed using the alignment marks for aligning to the probe pads. An additional package component is bonded to the reconstructed wafer through solder regions. The solder regions are physically joined to the top electrical connectors.
    Type: Application
    Filed: January 9, 2023
    Publication date: January 18, 2024
    Inventors: Cheng-Chieh Wu, Kuo-Lung Pan, Shu-Rong Chun, Hao-Yi Tsai, Po-Yuan Teng, Mao-Yen Chang, Cheng Yu Liu, Chia-Wen Lin
  • Publication number: 20240021772
    Abstract: An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes an epitaxial stack, a trench, a concave portion, a first contact structure, and a first electrode. The epitaxial stack includes a first semiconductor structure, an active structure on the first semiconductor structure, and a second semiconductor structure on the active structure, wherein the epitaxial stack has a first portion and a second portion, and the second semiconductor structure of the first portion is separated from the second semiconductor structure of the second portion. The trench is located between the first portion and the second portion. The concave portion is located in the first portion. The first contact structure is located in the concave portion. The first electrode covers the first contact structure. When the optoelectronic semiconductor device is operating, the first portion does not emit light.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 18, 2024
    Inventors: Ching-En Huang, Hao-Ming Ku, Shih-I Chen, Tzu-Ling Yang, Ya-Wen Lin, Chuang-Sheng Lin, Yi-Chia Ho
  • Publication number: 20240021034
    Abstract: A security authentication method is provided. In a step (a), a to-be-recognized image information and a to-be-recognized voice information about a user are provided. Then, a step (b) is performed to identify and judge whether the to-be-recognized image information and the to-be-recognized voice information comply with a registered image information and a registered voice information, respectively. In a step (c), if the judging condition of the step (b) is satisfied, a security information prompt signal is generated. In a step (d), a to-be-recognized security information is provided by the user. Then, a step (e) is performed to identify and judge whether the to-be-recognized security information complies with an abnormal warning information. In a step (f), if the judging condition of the step (e) is satisfied, an abnormal state warning and processing process is performed.
    Type: Application
    Filed: August 24, 2022
    Publication date: January 18, 2024
    Inventors: HSIU-WEN WANG, Chih-Wen Lin
  • Publication number: 20240019156
    Abstract: A differentiable physics model of a building is used that defines thermodynamic relationships between zones of the building and a heating, ventilation, and air-conditioning (HVAC) system. A physics-constrained, data driven model learns behaviors of controlled components of the HVAC system. For each of a series of times during online operation of the HVAC system, past state values are recorded representing a performance of the HVAC system in the building and past inputs to the HVAC system to maintain the states. The past state values and the past inputs are input into the differentiable physics model and the data driven model to: jointly update first parameters of the differentiable physics model and second parameters of the data driven model, e.g., using moving horizon estimation; and determine a current input to the controlled components, e.g., using model predictive control.
    Type: Application
    Filed: July 15, 2022
    Publication date: January 18, 2024
    Inventors: Saman Mostafavi, Harish Doddi, Yu-Wen Lin, David Schwartz
  • Publication number: 20240020112
    Abstract: Managing source code change set commits to decrease time to identify software bugs in versions of a software project is provided. An initial order of relevant commits corresponding to the software project is determined in a priority queue based on a weight of each respective commit of the relevant commits. The initial order of the relevant commits is adjusted in the priority queue based on a build distance between the relevant commits of affected source files. A particular commit having a highest priority ranking is selected in the priority queue for build and test. The build and the test of the particular commit having the highest priority ranking in the priority queue is executed.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Inventors: Ke Wen Lin, Xiong Hu Luo, Chaofan Qiu, Li Rong Yi
  • Patent number: 11876706
    Abstract: In some cases, once Fast Reroute (FRR) has taken place (e.g., for MPLS protection), a further FRR is undesirable, and even detrimental. A mechanism to prevent a further FRR, once such a further FRR is determined to be potentially harmful, is described.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: January 16, 2024
    Assignee: Juniper Networks, Inc.
    Inventors: Kireeti Kompella, Wen Lin, Kevin Wang
  • Publication number: 20230420413
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface; a redistribution layer (RDL) having a surface, wherein the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects; and a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Alois Nitsch, Han-Wen Lin, Yin-Ying Chen, Meng-Chi Lee, Andreas Dost, Hans Gerard Jetten
  • Publication number: 20230414577
    Abstract: The present disclosure relates to a biodegradable ocular implant comprising a biodegradable polymer containing a compound such as Edonentan, or a pharmaceutically acceptable salt thereof. Also disclosed are methods of treatment of ocular diseases with the biodegradable ocular implant and methods of preparation of the same.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Inventors: Cheng-Wen Lin, Angela Dawn Glendenning, Sevgi Gurkan
  • Publication number: 20230409385
    Abstract: A method, computer system, and a computer program product for improving debugging speed by rearranging debugging priority functions. In one embodiment, runtime input may be received about a program to be debugged. Feedback information is obtained about at least one similar program previously debugged. The compiling time information and runtime information are analyzed to determine a status of functions including one or more focused functions that will be used frequently and one or more unreachable functions that may never will be executed. A priority list of debugging functions is generated based on the feedback information, the runtime input and a function status. A plurality of debugging information are rearranged and parsed on the priority list prior to said program being debugged based on said debugging information.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Inventors: JIU FU GUO, Ke Wen Lin, Zheng Chen, Si Yuan Zhang
  • Publication number: 20230405070
    Abstract: A method for inhibiting immune responses, comprising administering to a subject in need thereof an effective amount of a pharmaceutical composition comprising salvigenin, and optionally cirsimaritin, rosmarinic acid, carvacrol, or a combination thereof.
    Type: Application
    Filed: May 26, 2023
    Publication date: December 21, 2023
    Inventors: Kung-Ming LU, Min-Liang KUO, Ching-Wen LIN
  • Publication number: 20230395436
    Abstract: Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Ming-Yuan Wu, Ka-Hing Fung, Min Jiao, Da-Wen Lin, Wei-Yuan Jheng
  • Publication number: 20230387073
    Abstract: An integrated circuit assembly may be formed with a bridge incorporated into at least one level structure of the integrated circuit assembly, which electrically interconnects at least two integrated circuit devices in another level structure of the integrated circuit assembly. In one example, the integrated circuit assembly may include a first level structure that comprises at least a first integrated circuit device and a second integrated circuit device, and a second level structure comprising at least one integrated circuit device electrically attached to the first integrated circuit device of the first level structure and the bridge forming an electrical attachment between the first integrated circuit device of the first level structure and the second integrated circuit device of the first level structure.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: Intel Corporation
    Inventors: Kai-Chiang Wu, Han-wen Lin
  • Publication number: 20230378142
    Abstract: A pixel package includes a base material, a circuit structure, light-emitting semiconductor elements, a non-light-emitting semiconductor element, and a light-transmitting adhesive layer. The base material has an upper surface, a lower surface, and a side surface. The circuit structure is buried in the base material and includes an first circuit layer exposed from the upper surface, bottom electrodes exposed from the lower surface, and a middle circuit layer between the upper circuit layer and the plurality of bottom electrodes and covered by the base material. The light-emitting semiconductor elements are on the upper surface and electrically connected to the circuit structure. The non-light-emitting semiconductor element is buried in the base material and directly connected to the middle circuit layer, and at least one outside surface is exposed. The light-transmitting adhesive layer covers the light-emitting semiconductor elements and is in direct contact with the base material.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 23, 2023
    Inventors: Li-Yuan HUANG, Tzu-Hsiang WANG, Chi-Chih PU, Ya-Wen LIN, Pei-Yu LI, Hsiao-Pei CHIU
  • Publication number: 20230378021
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Patent number: D1005960
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: November 28, 2023
    Assignee: Intex Marketing Ltd.
    Inventors: Zhi Xiong Huang, Ying Biao Zhang, Zheng Wen Lin
  • Patent number: D1011180
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: January 16, 2024
    Assignee: ZHONGSHAN WENSU HARDWARE PRODUCTS CO., LTD
    Inventors: Xue Lin, Wen Lin