Patents by Inventor Wen Lin

Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220143114
    Abstract: The present invention provides an active substance of Lactic Acid Bacteria, a composition comprising thereof and its use for promoting longevity, especially for increasing Cisd2 gene expression, reducing mitochondrial damage and delaying aging conditions such as nerve degeneration and sarcopenia.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: GRAPE KING BIO LTD.
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shin-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG
  • Patent number: 11328634
    Abstract: The projection device includes a light source, a liquid crystal on silicon (LCoS) panel, and a circuit. The circuit is configured to obtain a target image including a target pattern, and generate two content images. Each content image includes a duplicated pattern of the target pattern, and the duplicated patterns are off-axis shifted to the same coordinate when performing a computer-generated hologram (CGH) algorithm, so as to generate a phase image. The LCoS panel is driven according to the phase image to display a reconstructive image at a reconstructive distance.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: May 10, 2022
    Assignee: Himax Display, Inc.
    Inventors: Biing-Seng Wu, Chi-Wen Lin, Kuan-Hsu Fan Chiang
  • Patent number: 11319942
    Abstract: A compressor includes a motor body having a gas compressing motor, at least a pneumatic cylinder for compressing gas, and at least a cooling fan. The pneumatic cylinder comprises a cylinder support arranged on top of the compressing motor, a valve panel arranged on top of the cylinder support, a cylinder cover provided on top of the valve panel, and a piston connecting rod body slidably connected with the cylinder support. The heat dissipating channels, the gas channels, and the heat dissipating passages are arranged in series to jointly form a heat dissipation path, such that when the piston connecting rod body is driven by the compressing motor to conduct a gas compressing process in the cylinder support, the cooling fan is also driven to operate to drive the external gas to flow through the heat dissipation path and to flow out, so as to bring out the heat produced during the operation of the pneumatic cylinder and to achieve an effective heat dissipation.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: May 3, 2022
    Inventors: Yu-Wen Lin, Shi-An Sun
  • Patent number: 11311715
    Abstract: The disclosure provides a self-powered sheet which is configured to absorb a liquid content and to be applied on a human skin. The self-powered sheet includes a base layer and a plurality of electrically conductive inks. The base layer is configured to absorb the liquid content and adapted to be applied on the human skin. The base layer has a contact surface. The electrically conductive inks are disposed on the contact surface of the base layer. Each of the electrically conductive inks has a plurality of first electrodes and a plurality of second electrodes. When each of the first electrodes and each of the second electrodes are soaked in the liquid content, an electrical potential difference between one of the plurality of first electrodes and one of the plurality of second electrodes generates a current in the human skin.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 26, 2022
    Assignee: CYMMETRIK ENTERPRISE CO., LTD.
    Inventors: Wen-An Lin, Che-Ling Chang
  • Publication number: 20220118457
    Abstract: An integrated stage for holding rapid test reagent cards includes two U-shaped sidewalls opposite to each other, a first receiving space, a second receiving space, and an elastic sheet. The U-shaped sidewalls cooperatively define the first receiving space. The second receiving space is formed in the first receiving space and is lower than the first receiving space. The elastic sheet is arranged on a short side of the first receiving space. The first receiving space is used for allowing the integrated stage to hold a first rapid test reagent card. The second receiving space is used for allowing the integrated stage to hold a second rapid test reagent card. The integrated stage utilizes the elastic sheet to hold and fix the first rapid test reagent card or the second rapid test reagent card.
    Type: Application
    Filed: November 18, 2020
    Publication date: April 21, 2022
    Inventors: Yu-Cheng LIN, Wei-Chien WENG, Kai-Wen LIN
  • Patent number: 11310145
    Abstract: A disclosed method may include (1) identifying, by a PE router, a conditional advertisement policy that requires installation of at least one address of an active service appliance within a routing table to trigger advertising a route for the active service appliance to one or more additional PE routers, (2) inspecting the routing table for the installation of the address of the active service appliance, (3) determining, based at least in part on the inspection, that the address of the active service appliance is installed in the routing table, (4) determining that the PE router has satisfied the conditional advertisement policy due at least in part to the address of the active service appliance being installed in the routing table, and then in response, (5) directing the PE router to advertise the route to the additional PE routers. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 19, 2022
    Inventors: Wen Lin, John E. Drake
  • Patent number: 11307837
    Abstract: Embodiments of the present disclosure relate to runtime type identification (RTTI) of an object. In an embodiment, a computer-implemented method is disclosed. A class inheritance relationship between a plurality of classes in at least one source code section is generated. Respective type identifications are assigned to identify the classes in the class inheritance relationship. In accordance with presence of a first operation related to accessing a target pointer to an object of a target class of the classes, a type identification for the target class is caused to be recorded with at least one bit of a memory address of the target pointer that can be omitted in addressing the target pointer. RTTI is caused to be performed based on the class inheritance relationship and the at least one bit of the memory address of the target pointer. In other embodiments, a system and a computer program product are disclosed.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Zixuan Wu, Ke Wen Lin, Qing Shan Zhang, Kang Zhang
  • Publication number: 20220117093
    Abstract: A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventors: Pei-Chi HU, Jui-Chung LEE, Chi-Wen LIN
  • Patent number: 11302664
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: April 12, 2022
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 11304310
    Abstract: A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: April 12, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Pei-Chi Hu, Jui-Chung Lee, Chi-Wen Lin
  • Patent number: 11294292
    Abstract: An photolithographic apparatus includes a particle removing cassette selectively extendable from the processing apparatus. The particle removing cassette includes a wind blade slit and an exhausting slit. The wind blade slit is configured to direct pressurized cleaning material to a surface of the mask to remove the debris particles from the surface of the mask. The exhausting slit collects the debris particles separated from the surface of the mask and contaminants through the exhaust line. In some embodiments, the wind blade slit includes an array of wind blade nozzles spaced apart within the wind blade slit. In some embodiments, the exhausting slit includes array of exhaust lines spaced apart within the exhausting slit.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yang Lin, Da-Wei Yu, Li-Hsin Wang, Kuan-Wen Lin, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 11296908
    Abstract: Techniques are disclosed for an Ethernet Virtual Private Network (EVPN) Virtual Private Wire Service (VPWS) network with service interface-aware forwarding. In one example, a first network device signals to a second network device, using EVPN route advertisements, a multi-service service tunnel to transport network packets for a plurality of services. The services are identifiable by virtual local area network (VLAN) identifiers in the packets. The first network device is configured with a single transport interface for the service tunnel and the single transport interface is configured with respective service interfaces for the services. The first network device detects failure of a failed service interface of the service interfaces and outputs, in response to the failure, an EVPN route withdrawal message for the service tunnel that identifies the service corresponding to the failed service interface.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: April 5, 2022
    Assignee: Juniper Networks, Inc.
    Inventors: Wen Lin, Pankaj Kumar Gupta, Babu Singarayan, Sharmila Koppula, Manish Gupta, Kapil Arora
  • Publication number: 20220088000
    Abstract: Described herein are compounds and compositions for treating glaucoma and/or reducing intraocular pressure. Compositions may comprise an isoquinoline compound and a prostaglandin or a prostaglandin analog. Compounds described herein include those in which an isoquinoline compound is covalently linked to a prostaglandin or a prostaglandin analog, and those in which an isoquinoline compound and a prostaglandin free acid together form a salt.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Inventors: Casey Kopczynski, Cheng-Wen Lin, Jill Marie Sturdivant, Mitchell A. deLong
  • Publication number: 20220091639
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Patent number: 11282799
    Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Lin Wang, Ping-Chia Shih, Ming-Che Tsai, Kuei-Ya Chuang, Yi-Chun Teng, Po-Hsien Chen, Wan-Chun Liao
  • Patent number: 11280500
    Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 22, 2022
    Assignee: PIXART IMAGING INC.
    Inventors: Chih-Ming Sun, Ming-Han Tsai, Chiung-Wen Lin, Po-Wei Yu, Wei-Ming Wang, Sen-Huang Huang
  • Publication number: 20220082857
    Abstract: A hinge is provided. The hinge includes a first connection element, a second connection element, a first elastic element, and a second elastic element. The second connection element is connected to the first connection element. The first elastic element is connected to the first connection element. The second elastic element is connected to the first elastic element. The first elastic element drives the second elastic element to rotate relative to the second connection element. The first elastic element is rotatable between a first limit position and a second limit position. When the first elastic element is in the first limit position, the second elastic element is compressed.
    Type: Application
    Filed: January 4, 2021
    Publication date: March 17, 2022
    Inventors: Chun-Lung CHEN, Wen-Pei CHEN, Chia-Hui WU, Chia-Wen LIN
  • Patent number: 11276766
    Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Yin-Pin Wang, Kuo-Feng Yu, Da-Wen Lin, Jian-Hao Chen, Shahaji B. More
  • Publication number: 20220077166
    Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.
    Type: Application
    Filed: October 19, 2020
    Publication date: March 10, 2022
    Inventors: Ping-Chia SHIH, Kuei-Ya CHUANG, Chuang-Hsin CHUEH, Ming-Che TSAI, Wen-Lin WANG, Yi-Chun TENG, Ssu-Yin LIU, Wan-Chun LIAO
  • Patent number: 11264355
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Grant
    Filed: May 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin