Abstract: An integrated stage for holding rapid test reagent cards includes two U-shaped sidewalls opposite to each other, a first receiving space, a second receiving space, and an elastic sheet. The U-shaped sidewalls cooperatively define the first receiving space. The second receiving space is formed in the first receiving space and is lower than the first receiving space. The elastic sheet is arranged on a short side of the first receiving space. The first receiving space is used for allowing the integrated stage to hold a first rapid test reagent card. The second receiving space is used for allowing the integrated stage to hold a second rapid test reagent card. The integrated stage utilizes the elastic sheet to hold and fix the first rapid test reagent card or the second rapid test reagent card.

Abstract: Embodiments of the present disclosure relate to runtime type identification (RTTI) of an object. In an embodiment, a computer-implemented method is disclosed. A class inheritance relationship between a plurality of classes in at least one source code section is generated. Respective type identifications are assigned to identify the classes in the class inheritance relationship. In accordance with presence of a first operation related to accessing a target pointer to an object of a target class of the classes, a type identification for the target class is caused to be recorded with at least one bit of a memory address of the target pointer that can be omitted in addressing the target pointer. RTTI is caused to be performed based on the class inheritance relationship and the at least one bit of the memory address of the target pointer. In other embodiments, a system and a computer program product are disclosed.

Abstract: A disclosed method may include (1) identifying, by a PE router, a conditional advertisement policy that requires installation of at least one address of an active service appliance within a routing table to trigger advertising a route for the active service appliance to one or more additional PE routers, (2) inspecting the routing table for the installation of the address of the active service appliance, (3) determining, based at least in part on the inspection, that the address of the active service appliance is installed in the routing table, (4) determining that the PE router has satisfied the conditional advertisement policy due at least in part to the address of the active service appliance being installed in the routing table, and then in response, (5) directing the PE router to advertise the route to the additional PE routers. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.

Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.

Abstract: An photolithographic apparatus includes a particle removing cassette selectively extendable from the processing apparatus. The particle removing cassette includes a wind blade slit and an exhausting slit. The wind blade slit is configured to direct pressurized cleaning material to a surface of the mask to remove the debris particles from the surface of the mask. The exhausting slit collects the debris particles separated from the surface of the mask and contaminants through the exhaust line. In some embodiments, the wind blade slit includes an array of wind blade nozzles spaced apart within the wind blade slit. In some embodiments, the exhausting slit includes array of exhaust lines spaced apart within the exhausting slit.

Abstract: Techniques are disclosed for an Ethernet Virtual Private Network (EVPN) Virtual Private Wire Service (VPWS) network with service interface-aware forwarding. In one example, a first network device signals to a second network device, using EVPN route advertisements, a multi-service service tunnel to transport network packets for a plurality of services. The services are identifiable by virtual local area network (VLAN) identifiers in the packets. The first network device is configured with a single transport interface for the service tunnel and the single transport interface is configured with respective service interfaces for the services. The first network device detects failure of a failed service interface of the service interfaces and outputs, in response to the failure, an EVPN route withdrawal message for the service tunnel that identifies the service corresponding to the failed service interface.

Abstract: Described herein are compounds and compositions for treating glaucoma and/or reducing intraocular pressure. Compositions may comprise an isoquinoline compound and a prostaglandin or a prostaglandin analog. Compounds described herein include those in which an isoquinoline compound is covalently linked to a prostaglandin or a prostaglandin analog, and those in which an isoquinoline compound and a prostaglandin free acid together form a salt.

Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.

Abstract: A hinge is provided. The hinge includes a first connection element, a second connection element, a first elastic element, and a second elastic element. The second connection element is connected to the first connection element. The first elastic element is connected to the first connection element. The second elastic element is connected to the first elastic element. The first elastic element drives the second elastic element to rotate relative to the second connection element. The first elastic element is rotatable between a first limit position and a second limit position. When the first elastic element is in the first limit position, the second elastic element is compressed.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: Embodiments of the present disclosure relate to runtime type identification (RTTI) of an object. In an embodiment, a computer-implemented method is disclosed. A class inheritance relationship between a plurality of classes in at least one source code section is generated. Respective type identifications are assigned to identify the classes in the class inheritance relationship. In accordance with presence of a first operation related to accessing a target pointer to an object of a target class of the classes, a type identification for the target class is caused to be recorded with at least one bit of a memory address of the target pointer that can be omitted in addressing the target pointer. RTTI is caused to be performed based on the class inheritance relationship and the at least one bit of the memory address of the target pointer. In other embodiments, a system and a computer program product are disclosed.

Abstract: A wavelength conversion element, including a turntable, is provided. The turntable is configured to rotate along a central axis. The turntable has a first surface and a plurality of first turbulence portions and a plurality of second turbulence portions located on the first surface, wherein the first turbulence portions and the second turbulence portions are arranged by surrounding the central axis, a shape of each of the first turbulence portions is different from a shape of each of the second turbulence portions, and at least one of the second turbulence portions is arranged between two adjacent first turbulence portions of the first turbulence portions. A projector, including the wavelength conversion element, is further provided. The wavelength conversion element and the projector effectively improve the heat dissipation effect.

Abstract: A thermal module and a projector using the same are provided. The thermal module comprises a heat sink and a base. The heat sink comprises a bottom, a plurality of fins, a cover, and a plurality of side walls. The fins are disposed on the bottom, and each of the fins comprises a reference plane and a plurality of protrusions, wherein adjacent two of the protrusions are convex toward opposite directions with respect to the reference plane, and rows of through holes are formed by adjacent two protrusions along a flowing direction. The cover is disposed on the fins. The side walls are disposed between the bottom and the cover and surrounding the fins, wherein a liquid is capable of flowing through the heat sink by entering the inlet and exiting by the outlet of the side walls or the cover. The bottom of the heat sink is disposed on the base.

Abstract: A method for fast and convenient manufacture of liquid crystal display panels of different sizes without retooling provides an array substrate having a first display area of a first size. A closed-shaped sealant is coated onto the array substrate, the sealant defining a second display area of a second size, the second display area including an actual display area and an undesired display area adjacent to the actual display area and the sealant. Liquid crystals are applied in the second display area and sealing and coupling are carried out to obtain a liquid crystal cell, the liquid crystal cell being cut along an outer periphery of the sealant to obtain a working liquid crystal display panel of the desired size.