Patents by Inventor Wen Lin

Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8759943
    Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Tseng, Da-Wen Lin, Chien-Tai Chan, Chia-Pin Lin, Li-Wen Weng, An-Shen Chang, Chung-Cheng Wu
  • Patent number: 8754438
    Abstract: An LED comprises a substrate, a buffer layer, an epitaxial layer and a conductive layer. The epitaxial layer comprises a first N-type epitaxial layer, a second N-type epitaxial layer, and a blocking layer with patterned grooves sandwiched between the first and second N-type epitaxial layers. The first and second N-type epitaxial layers make contact each other via the patterned grooves. Therefore, the LED enjoys a uniform current distribution and a larger light emitting area. A manufacturing method for the LED is also provided.
    Type: Grant
    Filed: February 19, 2012
    Date of Patent: June 17, 2014
    Assignee: Advanced Optoelectronics Technology, Inc.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu, Chia-Hung Huang, Shun-Kuei Yang
  • Patent number: 8753980
    Abstract: A method of performing rapid thermal annealing on a substrate including heating the substrate to a first temperature in a rapid thermal annealing system having a front-side heating source and a backside heating source. The method further includes raising the temperature of the substrate from the first temperature to a second temperature greater than the first temperature. The backside heating source provides a greater amount of heat than the front-side heating source during the raising of the temperature of the substrate.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chii-Ming Wu, Da-Wen Lin
  • Publication number: 20140160641
    Abstract: An electronic apparatus including a housing, a touch-sensing module and a controller is provided. The touch-sensing module is embedded in the housing and includes a plurality of conductive sheets and an insulation material. The insulation material is combined with and electrically insulated from the conductive sheets. The controller is connected to the touch-sensing module, so as to identify the touch-sensing event occurring at the conductive sheets.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Applicant: HTC Corporation
    Inventors: I-Cheng Chuang, Yu-Jing Liao, Ying-Yen Cheng, Hung-Wen Lin
  • Patent number: 8749611
    Abstract: A video conference system built in an internet protocol (IP) network is provided. The system has: a multimedia capturing unit configured to photograph and output a first video signal; a DECT telephone configured to receive sounds and output a first audio signal; and a video conference terminal apparatus, including: an audio processing unit is an audio codec; a video processing unit is an video codec; and a network processing unit for transmitting a first network packet consisting of first audio/video streams generated by the audio/video processing units to the IP network, wherein the network processing unit receives a second network packet consisting of second audio/video streams from the IP network, wherein the second audio/video streams are decoded by the audio/video processing units, respectively, to generate second audio/video signals, which are displayed on the DECT telephone and a display apparatus, respectively.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Quanta Computer Inc.
    Inventors: Barry Lam, Chia-Yuan Chang, Rong-Quen Chen, Chi-Cheng Chang, Huan-Tang Wu, Chih-Wei Sung, I-Chung Chien, Chih-Yin Lin, Ting-Han Huang, Juin-Yi Huang, Hsin-Lun Hsieh, Chao-Chueh Chang, Kang-Wen Lin, Chia-Yi Wu
  • Patent number: 8751976
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 10, 2014
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8751551
    Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 10, 2014
    Assignee: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis, Volker Mauer, Henry Y. Lui, Suleyman Sirri Demirsoy, Hyun Yi
  • Patent number: 8747262
    Abstract: A jointed bat includes a barrel, a handle, and a glue. The barrel is tubular and has one end fixedly connected to a top cap and the other end having a tapered first joint portion. An opening is formed at the end of the first joint portion. The handle is tubular and has one end fixedly connected to a knob and the other end having a tapered resilient second joint portion. At least a relief slit is formed at an end of the second joint portion. A dam protrudes from the second joint portion and abuts against an inner wall of the first joint portion. The second joint portion penetrates the opening to fit inside the first joint portion. The glue is filled between and fixedly connected between the first and second joint portions. Therefore, requirements for precision in production of the barrel and the handle are reduced.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 10, 2014
    Inventors: Hung-Wen Lin, Ping-Hsueh Li
  • Patent number: 8742442
    Abstract: A method for patterning an epitaxial substrate includes: (a) forming an etch mask layer over an epitaxial substrate, and patterning the etch mask layer using a patterned cover mask layer to form the etch mask layer into a plurality of spaced apart mask patterns; and (b) etching the epitaxial substrate that is exposed from the mask patterns, and removing the mask patterns such that the epitaxial substrate is formed with a plurality of spaced apart substrate patterns.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 3, 2014
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Cheng-Hung Wei, Bo-Wen Lin, Ching-Yen Peng, Hao-Chung Kuo, Wen-Ching Hsu
  • Patent number: 8741592
    Abstract: The present invention provides methods of screening an agent for an activity in an isolated organ, e.g., eye, from a teleost, e.g., zebrafish. Methods of isolating eyes from zebrafish are provided. Methods of screening an agent for an ocular activity in the isolated eye are provided. Methods of screening an agent for an ocular activity in a model of ocular disease or disorder are provided. Methods of screening an agent for an ocular activity in the isolated eye and for screening the agent for cell death and/or toxic activity in the eye or other organ or tissue are provided. The invention further provides high throughput methods of screening agents for an activity in isolated eyes of zebrafish in multi-well plates.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 3, 2014
    Assignee: Phylonix Pharmaceuticals, Inc.
    Inventors: Patricia McGrath, Wen Lin Seng
  • Patent number: 8745550
    Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8742443
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer, a functional layer and a light generating layer. The buffer layer is located on a top surface of the substrate. The functional layer includes a plurality of high-temperature epitaxial layers and low-temperature epitaxial layers alternatively arranged between the buffer layer and light generating layer. A textured structure is formed in the low-temperature epitaxial layer. A SiO2 layer including a plurality of convexes is located on the textured structure to increase light extraction efficiency of the LED epitaxial structure. A manufacturing method of the LED epitaxial structure is also disclosed.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: June 3, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu
  • Patent number: 8740987
    Abstract: An implant including a substantially cohesive aggregate comprising bone-derived particles. Cohesiveness is maintained by a member of mechanical interlocking, engagement of adjacent bone-derived particles with one another through engagement with a binding agent, thermal bonding, chemical bonding, or a matrix material in which the bone-derived particles are retained. The aggregate is shaped as a one-dimensional or two-dimensional body.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: June 3, 2014
    Assignee: Warsaw Orthopedic, Inc.
    Inventors: Perry Geremakis, Jennifer Grasso, David Knaack, Jo-Wen Lin, Lawrence Shimp, Robert Waterman, John Winterbottom
  • Patent number: 8743027
    Abstract: An OLED driving circuit is provided. The OLED driving circuit comprises a switch transistor, a storage capacitor, a driving transistor and a control module. In a charging time period, a charging switch of the control module is conducted to connect the storage capacitor and a first voltage end and a data signal is transmitted from the switch transistor to the storage capacitor. In a memory time period, a memory switch of the control module is conducted to connect the storage capacitor and an OLED and the data signal is transmitted from the switch transistor to the storage capacitor. In a light-emitting time period, three light-emitting switches are conducted to connect the driving transistor to the storage capacitor, the first voltage end and the OLED.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: June 3, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Chi-Liang Wu, Po-Hsin Lin, Chin-Wen Lin, Ted-Hong Shinn
  • Publication number: 20140148280
    Abstract: A jointed bat includes a barrel, a handle, and a glue. The barrel is tubular and has one end fixedly connected to a top cap and the other end having a tapered first joint portion. An opening is formed at the end of the first joint portion. The handle is tubular and has one end fixedly connected to a knob and the other end having a tapered resilient second joint portion. At least a relief slit is formed at an end of the second joint portion. A dam protrudes from the second joint portion and abuts against an inner wall of the first joint portion. The second joint portion penetrates the opening to fit inside the first joint portion. The glue is filled between and fixedly connected between the first and second joint portions. Therefore, requirements for precision in production of the barrel and the handle are reduced.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Inventors: Hung-Wen LIN, Ping-Hsueh LI
  • Patent number: 8739080
    Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140141553
    Abstract: A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer totally covering the protrusions; forming a plurality of semiconductor islands on an upper surface of the un-doped GaN layer by self-organized growth, gaps being formed between two adjacent semiconductor islands to expose a part of the upper surface of the un-doped GaN layer; forming an n-type GaN layer on the exposed part of the upper surface of the un-doped GaN layer, the n-type GaN layer being laterally grown to totally cover the semiconductor islands; forming an active layer on an upper surface of the n-type GaN layer; and forming a p-type GaN layer on the active layer.
    Type: Application
    Filed: September 25, 2013
    Publication date: May 22, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: CHING-HSUEH CHIU, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
  • Patent number: 8729627
    Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Lung Cheng, Yen-Chun Lin, Da-Wen Lin
  • Publication number: 20140131727
    Abstract: A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer having an upper part covering top ends of the protrusions; forming a distributed bragg reflective layer on the un-doped GaN layer until the distributed bragg reflective layer totally covering the protrusions and the un-doped GaN layer; etching the distributed bragg reflective layer and the upper part of the un-doped GaN layer to expose the top ends of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the distributed bragg reflective layer. An LED chip formed by the method described above is also provided.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 15, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: CHING-HSUEH CHIU, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
  • Publication number: 20140131656
    Abstract: A light emitting diode chip includes a sapphire substrate and a plurality of carbon nano-tubes arranged on an upper surface of the sapphire substrate. Gaps are formed between two adjacent carbon nano-tubes to expose parts of the upper surface of the sapphire substrate. An un-doped GaN layer is formed on the exposed parts of the upper surface of the sapphire substrate and covers the carbon nano-tubes. An n-type GaN layer, an active layer and a p-type GaN layer are formed on the un-doped GaN layer in sequence. A method for manufacturing the light emitting diode chip is also provided.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 15, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: YA-WEN LIN, CHING-HSUEH CHIU, PO-MIN TU, SHIH-CHENG HUANG