Abstract: A display driving circuit includes a temperature compensation adjustment circuit, a control circuit, a full bridge circuit, and a transformation circuit. The temperature compensation adjustment circuit provides a current signal for the control circuit. The value of the current signal changes along with environment temperature changes. The control circuit controls the full bridge circuit based on the current signal. An output voltage signal of the full bridge circuit decreases as the current signal increases, and when the environment temperature decreases. The transformation circuit amplifies the output voltage signal of the full bridge circuit to drive a display.

Abstract: Methods and systems of verifying an animation applied in a mobile device may include a timer module that is programmed to time-slice the animation into multiple scenes at predetermined time points along a timeline of the animation. A first capture module is programmed to capture actual data of each scene at each of the time points while the animation is running. A first comparison module is programmed to compare the actual data of each scene with expected data of the corresponding scene to determine whether the actual data of each scene matches the expected data of the corresponding scene. A first output module is programmed to generate a verification failure if the actual data of any scene does not match the expected data of the corresponding scene, and generate a verification success if the actual data of each scene matches the expected data of the corresponding scene.

Abstract: A control circuit includes a plurality of shift register stages. Each shift register stage is capable of outputting an individual output signal. The output signal is utilized to be a driving signal of next shift register stages. Each shift register stage comprises a transistor for receiving a clear signal CLR. The residual charges of the shift register stage can be released when the clear signal CLR is in a high voltage level. The clear signal CLR is enabled during a non-blanking time of a liquid crystal display (LCD). Each current register stage can use an output signal of another shift register stage which is apart from the current shift register stage by a predetermined interval as the clear signal CLR. The clear signal CLR is used to release the residual charges of the shift register stage before the shift register stage outputs its own output signal.

Abstract: A plurality of differently configured bone spinal implants for insertion in a spine have a cylindrical bore for receiving an insertion head stud. A plurality of instruments are disclosed each of which have a first connection element which is either a male or female member such as e.g., a ball and socket, a cylinder and socket and so on for forming either a stationary or articulating interchangeable joint for a plurality of disc processing heads or implant insertion heads. The plurality of disc space processing heads or implant insertion heads have a complementary second joint member for interchangeable attachment to the first connection element. The implant insertion heads or disc processing heads have different configurations for different shaped implants.

Abstract: The present invention provides a lead-free brass alloy, including 0.3 to 0.8 wt % of aluminum, 0.01 to 0.4 wt % of bismuth, 0.05 to 1.5 wt % of iron and more than 96 wt % of copper and zinc, wherein the copper is present in an amount ranging from 58 to 75 wt %. The brass alloy of the present invention meets the standard of the environmental regulation, wherein the lead content is less than 0.25 wt % based on the weight of the alloy. Further, the brass alloy of the present invention has 0.05 to 1.5 wt % of iron and less than 0.4% of bismuth, so as to lower production cost, eliminate cracks and increase production yield.

Abstract: A clamshell device having a dual accelerometer detector includes a first keyboard portion including a first accelerometer, a second display portion including a second accelerometer, a hinge for coupling the first portion to the second portion, and circuitry coupled to the first and second accelerometers for providing an output signal in response to the position of the first and second portions of the clamshell device. The output signal is provided to indicate a shutdown or standby mode, tablet operation mode, a partially shut or power savings mode, a normal operating mode, or an unsafe operating mode.

Abstract: Methods of-identifying a basal or luminal phenotype of a cell, comprising detecting expression of one or more of a set of predictive biomarker genes or proteins that identify the cell as having a basal or luminal cancer subtype and compositions for treating identified basal or luminal cancers.

Abstract: A display panel is used with an image display system. The display panel includes a light-transmissive substrate, a gate insulating layer, a gate conductor, a first light-shielding structure, a channel layer and a second light-shielding structure. The gate insulating layer is formed over the light-transmissive substrate. The gate conductor and the first light-shielding structure are made of the same material, formed over the gate insulating layer, and electrically isolated from each other. The first light-shielding structure has a hollow portion. The channel layer and the second light-shielding structure made of the same material and formed over the light-transmissive substrate but under the gate insulating layer. The second light-shielding structure is disposed under the hollow portion of the first light-shielding structure.

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.

Abstract: A patterned sapphire substrate manufacturing method uses two-section dip etching procedure to improve the lateral etching rate at each etching position, so as to produce a concave-convex pattern composed of a plurality of triangular pyramid structures protruded from a surface onto an upper surface of a sapphire substrate, such that less planar area of the sapphire substrate surface will remain, and a mixed solution of sulfuric acid and phosphoric acid is used in a first dip etching step, and pure phosphoric acid or a mixed solution of sulfuric acid and phosphoric acid is used in a second dip etching step for etching the sapphire substrate to control the inclination of each triangular pyramid structure precisely, and providing a better light extraction rate for later manufactured light emitting diodes.

Abstract: A method for accessing a Flash memory including a plurality of blocks includes: selectively programming a page in a first block of the blocks; when a status of the Flash memory is abnormal, determining whether a number of error bits is less than a predetermined value; and when the number of error bits is not less than the predetermined value, moving the first block. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. In addition, when the number of error bits is not less than the predetermined value, the controller that executes the program code by utilizing the microprocessor moves the first block.

Abstract: An image sensing module includes a printed circuit board, an image sensor, and a color filter exchanging system. The image sensor positioned between the printed circuit board and the color filter exchanging system is assembled on the printed circuit board. The color filter exchanging system aligning with the image sensor fastens to the printed circuit board. The color filter exchanging system includes a stand, a driving module and a filter assembly. The stand fastening to the printed circuit board defines an opening revealing the image sensor. The driving module slides the filter assembly within the stand. The filter assembly includes a frame and a visible light bandpass filter and an infrared bandpass filter assembled to the frame. In different modes, the driving module drives the filter assembly so that the visible light bandpass filter or the infrared bandpass filter aligns with the image sensor by way of the opening.

Abstract: The present invention provides an environmental friendly brass alloy, including 0.4 to 0.8 wt % of aluminum; 0.6 to 1.6 wt % of nickel; 0.8 to 2.0 wt % of tin; more than 95.6 wt % of copper and zinc; and less than 0.1 wt % of iron, lead, phosphorous and impurities, wherein the copper is present in an amount ranging from 60 to 68 wt %.

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract: A method for fabricating a bi-polar plate of a fuel cell and the bi-polar plate thereof are presented. A graphite film is formed first. Next, a polymeric material added with electrically conductive powder is coated on a surface of a metal substrate. The graphite film is disposed on the polymeric material and the polymeric material is hardened to form an adhesive layer, such that the graphite film is attached on the surface of the metal substrate.

Abstract: A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address.

Abstract: A method for enhancing performance of accessing a Flash memory, which includes a plurality of blocks and is positioned in a memory device, includes: during writing data into the Flash memory, establishing/updating at least one linking table in a random access memory (RAM) of the memory device, wherein regarding the Flash memory, the linking table indicates linking relationships between logical addresses and physical addresses, or indicates linking relationships between physical addresses and logical addresses; and writing the linking table into the Flash memory only when it is detected that a flush cache command is sent from a host device. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory.

Abstract: The present invention provides a low-lead copper alloy, which includes 0.05 to 0.3 wt % of lead, 0.3 to 0.8 wt % of aluminum, 0.01 to 3 wt % of bismuth, 1 to 4 wt % of silicon, 0.1 to 1 wt % of tin, and more than 93.6% of copper and zinc, wherein copper is in an amount ranging from 61 to 78 wt %. The low-lead copper alloy of the present invention has excellent toughness and processability, and can provide increased resistance in an environment with a high concentration of chlorine ions.