Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230393092
    Abstract: A semiconductor device includes a substrate, an interconnect, and a sensor. The substrate includes devices therein and has a front side and a rear side opposite to the front side. The interconnect is disposed on the front side and electrically coupled to the devices. The sensor is disposed over the substrate and in the interconnect, and includes a sensing element and a reference element. The sensing element is disposed in a topmost layer of the interconnect and exposed therefrom, where the sensing element is electrically coupled to a first device of the devices through the interconnect. The reference element is disposed in the topmost layer of the interconnect and exposed therefrom, where the reference element is laterally spaced from the sensing element and is electrically coupled to a second device of the devices through the interconnect.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Lee, Chung-Liang Cheng, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • 3D capacitor and method of manufacturing same
    Patent number: 11837646
    Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • 3D CAPACITOR AND METHOD OF MANUFACTURING SAME
    Publication number: 20230387248
    Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Chi-Wen LIU, Chao-Hsiung WANG
  • Call record synchronization method, cloud platform, and terminal
    Patent number: 11832150
    Abstract: Embodiments of the present invention relate to a call record synchronization method, a cloud platform, and a terminal. The method includes: detecting, by a first terminal, an input operation for requesting to display a call record; and after the first terminal detects the input operation, displaying, by the first terminal, a merged call record, where the merged call record is a call record obtained after merging of a call record of the first terminal and a call record of a second terminal, and the merged call record includes a device identifier of the first terminal and/or a device identifier of the second terminal. According to the embodiments of the present invention, a user can use the merged call record to identify call answering or making statuses on a plurality of terminals, without querying a plurality of call records. This improves user experience.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 28, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tao Li, Feng Li, Chenjian Zhao, Shaolong Wang, Wen Liu, Chunlai Feng, Xiaolin Li, Xutao Gao, Wenhua Li
  • METHOD FOR DETERMINING 224Ra IN SEDIMENT BY USING PULSE IONIZATION CHAMBER EMANOMETER
    Publication number: 20230375725
    Abstract: Disclosed is a method for determining 224Ra in a sediment by using a pulse ionization chamber emanometer, which belongs to the technical field of analysis and measurement. A pulse ionization chamber emanometer (PIC), a new emanometer, is used. Based on the half-life characteristics of different radon isotopes, one can separate the 220Rn activity from the total counts by dual counting. The resulting 220Rn measurement then can be used to determine the 224Ra activity in sediment according to the principle of secular radioactive equilibrium.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 23, 2023
    Inventors: Guangquan Chen, Wen Liu, Shibin Zhao, Chunqian Li, Jinjia Guo, Yancheng Wang, Bochao Xu, Xiaofei Yin, Shan Sun
  • INTEGRATED CIRCUIT STRUCTURE AND METHOD WITH SOLID PHASE DIFFUSION
    Publication number: 20230369409
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • BIOSENSOR
    Publication number: 20230366851
    Abstract: A biosensor including a first sensor, a second sensor, a patterned dielectric layer and a cover is provided. The first sensor includes a first voltage-reference device and a first bio-sensing device. The second sensor is disposed adjacent to the first sensor, the second sensor includes a second voltage-reference device and a second bio-sensing device, the first sensor is spaced apart from the second sensor by a lateral distance, and the lateral distance is greater than a half of an average lateral dimension of the first voltage-reference device and the second voltage-reference device. The patterned dielectric layer includes sensing wells located above the first voltage-reference device, the first bio-sensing device, the second voltage-reference device and the second bio-sensing device. The cover includes fluid channels communicating with the sensing wells.
    Type: Application
    Filed: May 16, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Lee, Katherine H CHIANG, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • MULTI-CHIP PACKAGES AND METHODS OF FORMING THE SAME
    Publication number: 20230369287
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Organic light-emitting diode display panels with moisture blocking structures
    Patent number: 11818912
    Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. The thin-film circuitry may be formed in thin-film transistor (TFT) layers and the organic light-emitting diodes may include anodes and cathodes and an organic emissive layer formed over the TFT layers between the anodes and cathodes. The organic emissive layer may be formed via chemical evaporation techniques. The display may include moisture blocking structures such as organic emissive layer disconnecting structures that introduce one or more gaps in the organic emissive layer during evaporation so that any potential moisture permeating path from the display panel edge to the active area of the display is completely terminated.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 14, 2023
    Assignee: Apple Inc.
    Inventors: Tsung-Ting Tsai, Abbas Jamshidi Roudbari, Chuan-Sheng Wei, HanChi Ting, Jae Won Choi, Jianhong Lin, Nai-Chih Kao, Shih Chang Chang, Shin-Hung Yeh, Takahide Ishii, Ting-Kuo Chang, Yu Hung Chen, Yu-Wen Liu, Yu-Chuan Pai, Andrew Lin
  • SEMICONDUCTOR DEVICE
    Publication number: 20230361019
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a wafer, powering redistribution layers, and grounding redistribution layers. The powering redistribution layers are disposed on the wafer. The grounding redistribution layers are disposed on the wafer, in which each of the powering redistribution layers and a corresponding one of the grounding redistributions layers form a capacitor.
    Type: Application
    Filed: May 3, 2022
    Publication date: November 9, 2023
    Inventor: Fang-Wen LIU
  • Semiconductor Device and Method of Forming the Same
    Publication number: 20230361181
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Intelligent power module packaging structure
    Patent number: 11810835
    Abstract: An intelligent power module packaging structure includes an insulated heat dissipation substrate, a plurality of power devices, a control chip, a lead frame, and an encapsulant. The insulated heat dissipation substrate has a first surface and a second surface opposite to the first surface. The power devices are disposed on the first surface. The control chip is disposed on the first surface. The control chip provides a gate driver function for driving the power devices and a pulse width modulation function. The lead frame is bonded onto the first surface. The power devices are electrically connected to the control chip and the lead frame. The encapsulant at least encapsulates the power devices, the control chip, and a portion of the lead frame, and the second surface is entirely or partially exposed outside the encapsulant.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 7, 2023
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES
    Publication number: 20230352352
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 2, 2023
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Method and electronic device for saving power applied to a router
    Patent number: 11805054
    Abstract: A method of routing data packets for a router is provided. The router includes a software network address translator (NAT) and a hardware NAT. The method includes routing, by the software NAT, a first data packet based on a routing rule stored in the software NAT, wherein the software NAT has a routing rule removing function to remove the routing rule stored in the software NAT; sending, by the software NAT, the routing rule to the hardware NAT; storing the routing rule, by the hardware NAT, in the hardware NAT; and routing, by the hardware NAT instead of the software NAT, a second data packet based on the routing rule stored in the hardware NAT. The routing rule removing function of the software NAT for the routing rule stored in the software NAT is disabled.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: October 31, 2023
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hua Huang, Ming-Jun Lin, Huei-Jing Yang, Kai-Wen Liu, Yuan-Ting Huang
  • IMS CALL ESTABLISHING METHOD AND ELECTRONIC DEVICE AND USER EQUIPMENT THEREOF
    Publication number: 20230344876
    Abstract: An IP Multimedia Subsystem (IMS) call establishing method is provided. The IMS call establishing method is applied to an electronic device which supports IMS service. The IMS call establishing method includes the steps of establishing a network connection between the electronic device and a client device; when the client device dials an IMS call, the electronic device obtains call information of the IMS call through the network connection; and the electronic device establishes the IMS call based on the call information of the IMS call.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Inventors: Kai-Wen LIU, Po-Chun LEE, Yuan-Ting HUANG, Yu-Hua HUANG
  • MODULE AND SYSTEM FOR CONTROLLING PHOTOVOLTAIC STRINGS TO PERFORM DOMINO-TYPE AUTOMATIC SNOW MELTING
    Publication number: 20230344382
    Abstract: Provided is a system for controlling photovoltaic strings to perform Domino-type automatic snow melting, including a controller, M photovoltaic strings and a photovoltaic power supply control module; the 1st to (k?1)th photovoltaic strings supply power to the kth photovoltaic string, in response to the kth photovoltaic string being in a load mode, 2?k?M. The M photovoltaic strings are correspondingly connected to M photovoltaic interfaces of the photovoltaic power supply control module; the controller is connected to the photovoltaic power supply control module, and is configured to control the working state of the photovoltaic power supply control module.
    Type: Application
    Filed: November 8, 2019
    Publication date: October 26, 2023
    Inventors: Jianan Zheng, Wen Liu, Jan Justus Ingenhoff, Wenjun Liu, Xinyu Zhang
  • Package structure
    Patent number: 11798898
    Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Wen Lee, Hsien-Wen Liu, Shin-Puu Jeng
  • Strained nanowire CMOS device and method of forming
    Patent number: 11798989
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • METHOD AND ELECTRONIC DEVICE FOR SAVING POWER APPLIED TO A ROUTER
    Publication number: 20230336472
    Abstract: A method of routing data packets for a router is provided. The router includes a software network address translator (NAT) and a hardware NAT. The method includes routing, by the software NAT, a first data packet based on a routing rule stored in the software NAT, wherein the software NAT has a routing rule removing function to remove the routing rule stored in the software NAT; sending, by the software NAT, the routing rule to the hardware NAT; storing the routing rule, by the hardware NAT, in the hardware NAT; and routing, by the hardware NAT instead of the software NAT, a second data packet based on the routing rule stored in the hardware NAT. The routing rule removing function of the software NAT for the routing rule stored in the software NAT is disabled.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Yu-Hua HUANG, Ming-Jun LIN, Huei-Jing YANG, Kai-Wen LIU, Yuan-Ting HUANG
  • Profile Download Method and Device
    Publication number: 20230328509
    Abstract: A profile download method includes a primary device obtaining an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID. The primary device receives the profile download information from the mobile operator server and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and where the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 12, 2023
    Inventors: Feng Li, Wen Liu, Chunlai Feng, Tao Li, Xiaolin Li, Xutao Gao, Wenhua Li