Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A manufacturing method of a tool surface mark includes a first cleaning step, a first electroplating step, an ionized water cleaning step, a drying step, a printing step, a second cleaning step and a second electroplating step. In the first electroplating step, the surface of the tool is electroplated to form a first protective layer on the surface of the tool. In the ionized water cleaning step, ionized water is sprayed on the surface of the tool and the ions in the ionic water are adhered to the pores of the first protective layer to form an ion-protective coating. In the second electroplating step, the surface of the tool is electroplated with nickel so that a second protective layer is formed on the surface of the tool. The ion-protective coating can enhance the adhesion of the printing pattern and make it difficult for the printing pattern to fall off.

Abstract: A manufacturing method of a tool surface mark includes a first cleaning step, a first electroplating step, a second cleaning step, a drying step, a printing step, a cation removal step, and a second electroplating step. In the first electroplating step, the surface of the tool is electroplated, and a first protective layer is formed on the surface of the tool. In the cation removal step, the tool is placed into an electrolyte and then electrically connected to an anode, the anode is electrically energized, and metal cations on the surface of the tool and on the printing pattern are dissolved. In the second electroplating step, the surface of the tool is electroplate at potions without the printing pattern to form a second protective layer. The yield of the printing pattern increases and the printing pattern does not easy peel off.

Abstract: An RF signal processing device includes multiple first signal receive paths receiving multiple first signals, multiple second signal receive paths receiving multiple second signals and a radio transceiver. The radio transceiver includes a first signal-processing circuit designed for processing the first signals, a second signal-processing circuit designed for processing the second signals, multiple first receive ports coupled to the first signal-processing circuit, multiple second receive ports coupled to the second signal-processing circuit, a first switch and a tunnel device. The first switch is coupled between at least one first receive port and the first signal-processing circuit. The tunnel device is coupled between the first switch and the second signal-processing circuit. The at least one first receive port coupled to the first switch is utilized to receive the first signal or the second signal.

Abstract: Intelligent image parsing for anatomical landmarks and/or organs detection and/or segmentation is provided. A state space of an artificial agent is specified for discrete portions of a test image. A set of actions is determined, each specifying a possible change in a parametric space with respect to the test image. A reward system is established based on applying each action of the set of actions and based on at least one target state. The artificial agent learns an optimal action-value function approximator specifying the behavior of the artificial agent to maximize a cumulative future reward value of the reward system. The behavior of the artificial agent is a sequence of actions moving the agent towards at least one target state. The learned artificial agent is applied on a test image to automatically parse image content.

Abstract: Provided herein are methods and compositions related to a retinoid receptor-selective pathway. As described herein, this pathway can be targeted to manipulate a tumor microenviroment. For example, the methods and compositions described herein can be used to induce apoptosis in a cancer cell. Further, the compositions described herein, including Sulindac and analogs thereof, can be used to target this pathway for the treatment or prevention of cancer in human patients.

Abstract: A handle structure including a base portion, a stop portion and a grip potion is provided. The grip portion is connected between the base portion and the stop portion. The handle structure has a cavity therein, the cavity has a bottom surface, and the bottom surface of the cavity is inclined to an axial direction of the grip potion.

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.

Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

Abstract: An image content commenting method and a related image management system can be utilized to establish a commenting record about partial content of an image stream. The image content commenting method includes reading a coordinate value of a cursor within a first image frame of the image stream, selecting a pattern object inside the first image frame according to the coordinate value, establishing connection between a first bookmark and the pattern object, and identifying the pattern object from a second image frame of the image stream and then connecting the first bookmark with the pattern object inside the second image frame.

Abstract: Provided are a plug and an electrical connector component. The plug includes an insulating body, a circuit board fixed to the insulating body, and a cable electrically connected with the circuit board and extending backwards from the insulating body. The insulating body includes a body part and a mating part which extends forwards from the body part; the circuit board has an inserting part that protrudes forwards out of the mating part; metal contact pieces are distributed on upper and lower surfaces of the inserting part; the insulating body is provided with a pair of baffle plates extending forwards from the body part; a pair of the baffle plates are respectively arranged on left and right sides of the mating part; and a limiting groove configured to guide the insertion of the plug with the socket is formed between each of the baffle plates and the mating part.

Abstract: A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring layer, and forming an encapsulating layer to cover the electronic component, thereby allowing the single wiring layer to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path. The present invention further provides a package structure thus fabricated.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

Abstract: Provided in the present invention are a class of Lincomycin biosynthetic intermediates and a preparation method and use thereof. Specifically provided are Lincomycin biosynthetic intermediates obtained from the genetic modification of a Lincomycin producing bacterium, and a method for the production thereof through fermentation and purification through separation.

Abstract: A fixed-line trimmer head for a rotary trimmer device includes the upper portion having a periphery, wherein the upper portion has a plurality of openings spaced from the periphery; and a plurality of mechanisms. Each mechanism can hold a strip of line and includes a post portion disposed through one of the openings in the upper portion, and a flange disposed at one end of the post portion and sandwiched between the upper portion and lower portion of the trimmer head to prevent vertical movement of the mechanism. The post portion includes two line channels, each line channel defining a passageway to receive the same strip of line, wherein at least one of the line channels is curved such that any portion of the strip of line being received through the passageway of that line channel is bent at that portion of the strip of line away from the second line channel while passing through that at least one line channel that is curved.

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.