Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180097097
    Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 5, 2018
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9935011
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20180090570
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 29, 2018
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 9930797
    Abstract: A latch mechanism capable of unlocking a first electronic module and a second electronic module separately includes an operating component, a base, a first moving component, a second moving component, a first latch component, and a second latch component. The operating component moves relative to the base along different directions to selectively drive one of the first moving component and the second moving component. When the first moving component is moved to drive the first pivoting component to pivot, the first latch component can be disengaged from the first electronic module, which unlocks the first electronic module. When the second moving component is moved to drive the second pivoting component to pivot, the second latch component can be disengaged from the second electronic module, which unlocks the second electronic module. It allows users to replace the first electronic module or the second electronic module separately.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: March 27, 2018
    Assignee: Wistron Corporation
    Inventors: Che-Wen Liu, I-Chun Chen, Mei-Shan Wu
  • Patent number: 9929245
    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang, Carlos H. Diaz
  • Publication number: 20180080838
    Abstract: A pressure sensing array includes a plurality of pressure sensing units and a control unit. Each of the pressure sensing units includes a plurality of first electrode blocks and a plurality of second electrode blocks. The second electrode blocks are arranged in a staggered manner along a first direction or a second direction, in which the first direction is substantially perpendicular to the second direction. The control unit is coupled to the pressure sensing units and used for controlling the first electrode blocks and the second electrode blocks of the each of the pressure sensing units to be turned on or off respectively.
    Type: Application
    Filed: July 26, 2017
    Publication date: March 22, 2018
    Inventors: Chi-Cheng CHEN, Gui-Wen LIU
  • Publication number: 20180083103
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 22, 2018
    Inventors: Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9923094
    Abstract: A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer. The recessing forms a trench disposed between sidewall portions of the spacer layer. At least a portion of the sacrificial layer is removed, and a source/drain region is formed in the trench.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • Patent number: 9922837
    Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
  • Publication number: 20180077274
    Abstract: A portable device can transmit information through one of a mobile phone network and an Internet, wherein the portable device includes a text-based communication module to allow a user may synchronously transmit or receive data through a local area network, wherein the data is text, audio, video or the combination thereof. The text-based communication module of the portable device includes a text-to-speech recognition module used to convert a text data for outputting the text data by vocal, and a read determination module for determining read target terminals and unread target terminals when a user of the portable phone device activates the read determination module.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 15, 2018
    Inventors: Chi-Wen LIU, Ching-Yu CHANG, Kuo-Ching CHIANG
  • Patent number: 9917178
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 9915421
    Abstract: The present invention discloses a saturated water explosive device, including a water intake pipe, a flow splitter for splitting a high-pressure liquid, a flow baffle for baffling the high-pressure liquid, a heat receiver having a cavity defined inside, a pillar connected with the heat receiver by a micro-channel wherein the high-pressure liquid is heated to be high-temperature saturated water, and a heat source for heating the cavity. High-pressure water is heated to produce high-temperature high-pressure saturated water, and then by using the saturated water explosive device of the present invention, the produced high-temperature high-pressure saturated water instantaneously explodes as being heated, and a high-temperature high-pressure steam flow is produced due to rapid vaporization, and expansion and is used as a power source.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: March 13, 2018
    Assignee: TAIZHOU DAJIANG IND. CO., LTD.
    Inventors: Gui-Wen Liu, Ming-Jun Yang, Jin-Quan Huang
  • Publication number: 20180069114
    Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 8, 2018
    Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
  • Publication number: 20180061642
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy comprising components of the first metal layer, second metal layer, and the semiconductor substrate.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chung-Chun HSU, Wei-Chun CHI
  • Publication number: 20180061988
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Application
    Filed: October 24, 2017
    Publication date: March 1, 2018
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Patent number: 9906634
    Abstract: A portable device can transmit information through one of a mobile phone network and an Internet, wherein the portable device includes a text-based communication module to allow a user may synchronously transmit or receive data through a local area network, wherein the data is text, audio, video or the combination thereof. The text-based communication module of the portable device includes a text-to-speech recognition module used to convert a text data for outputting the text data by vocal, and a read determination module for determining read target terminals and unread target terminals when a user of the portable phone device activates the read determination module.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: February 27, 2018
    Inventors: Chi Wen Liu, Ching Yu Chang, Kuo Ching Chiang
  • Patent number: 9905467
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20180051051
    Abstract: A method for preparing a precursor of gene expression probe is revealed. First prepare 2-deoxy-2-fluoro-3,5-di-O-benzoyl-?-D-arabinofuranosyl bromide and 2,4-bis-O-(trimethylsilyl)-5-bromouracil respectively. Then use 2-deoxy-2-fluoro-3,5-di-O-benzoyl-?-D-arabinofuranosyl bromide and 2,4-bis-O-(trimethylsilyl)-5-bromouracil to perform a coupling reaction and get a 1-(3,5-di-O-benzoyl-2-deoxy-2-fluoro-?-D-arabinofuranosyl)-5-bromouracil. Next use 1-(3,5-di-O-benzoyl-2-deoxy-2-fluoro-?-D-arabinofuranosyl)-5-bromouracil generated and hexabutylditin to perform a substitution reaction in an anhydrous 1,4-dioxane solution and get 1-(3,5-di-O-benzoyl-2-deoxy-2-fluoro-?-D-arabinofuranosyl)-5-tributylstannyl)uracil. At last carry out debenzoylation of 1-(3,5-di-O-benzoyl-2-deoxy-2-fluoro-?-D-arabinofuranosyl)-5-tributylstannyl)uracil to get 5-tributylstannyl-1-(2-deoxy-2-fluoro-?-D-arabinofuranosyl)uracil (FSAU), a precursor of gene expression probe.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: SHOW-WEN LIU, CHENG-FANG HSU, YU CHANG
  • Patent number: 9899489
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 9899537
    Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 20, 2018
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xian-Rui Chang