Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180190796
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20180188853
    Abstract: A data transmission method applied to a touch panel includes: determining an overlapped quantity of at least one first touch electrode pad and at least one second touch electrode pad that are electrically coupled to each other; determining a transmission bit number according to the overlapped quantity; and making the at least one first touch electrode pad transmit at least one data signal to the at least one second touch electrode pad according to the transmission bit number and a transmission frequency, where the at least one first touch electrode pad is configured on a first electronic apparatus, and the at least one second touch electrode pad is configured on a second electronic apparatus.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 5, 2018
    Inventors: Shan-Kang CHEN, Gui-Wen LIU
  • Patent number: 10010549
    Abstract: The present invention provides for compounds of Formula I-I and embodiments and salts thereof for the treatment of diseases (e.g., neurodegenerative diseases). R1, R2, R3, X1, X2, A and Cy variable in Formula I-I all have the meaning as defined herein.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 3, 2018
    Assignee: Genentech, Inc.
    Inventors: Anthony Estrada, Liting Dong, Kevin X. Chen, Paul Gibbons, Malcolm Huestis, Terry Kellar, Wen Liu, Changyou Ma, Joseph Lyssikatos, Alan Olivero, Snahel Patel, Daniel Shore, Michael Siu
  • Publication number: 20180182151
    Abstract: According to an embodiment of the present invention, a computer-implemented method for modeling text-to-articulatory movement conversion is provided. In the method, text features are generated for a plurality of texts, wherein the text feature comprises a phoneme. Articulatory features are determined for the plurality of texts from a plurality of audio signals and a plurality of visual signals, wherein the audio signals record speeches of the plurality of texts, the visual signals record three-dimensional images of an articulator when speaking the plurality of texts, and the articulatory features indicate articulatory positions of the articulator in the speeches. A text-to-articulatory movement model is established with the text features as inputs and the articulatory features as outputs.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Inventors: Wen LIU, Qin SHI, Shi Lei ZHANG, Peng Cheng ZHU
  • Publication number: 20180182673
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: February 26, 2018
    Publication date: June 28, 2018
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20180181572
    Abstract: An online system ranks topic-groups for users and presents content items in topic-based feeds. A topic group corresponds to one or more topic(s) and can be used to generate a feed for presenting the content items related to the topic(s). For a particular user, the topic groups are ranked according to the likelihood of the user interacting with content items included in the topic groups. The topic groups are ranked using information of the users and/or users' historical interaction data such as click-based interaction data, post-based interaction data, or engagement-based interaction data. The online system generates and provides a user interface for presenting the topic groups to the client device. Content items that are related to the topic(s) corresponding to the topic group are presented in each topic-based feed such that the user can switch between different topic-based feeds.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Shengbo Guo, Annie Hsin-Wen Liu, David Vickrey, Khalid Bakry El-Arini
  • Publication number: 20180184354
    Abstract: A dynamic crossband link method is provided, which includes utilizing a local forwarding module to transmit and receive packet data to and from a client device via a first frequency band; obtaining a plurality of communication quality indicators corresponding to a plurality of uplink forwarding modules; and determining to transmit the packet data to a wireless access device and receive the packet data from the wireless access device via one of the plurality of uplink forwarding modules according to the plurality of communication quality indicators.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Chia-Ching Huang, Yi-Wen Liu
  • Patent number: 10008603
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Publication number: 20180174918
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 21, 2018
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • Publication number: 20180175164
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; a fin structure including one or more fins formed on the semiconductor substrate; an insulator material formed between each of the one or more fins; a dielectric layer formed on a first portion of the fin structure; a first electrode formed on the dielectric layer; spacers formed on sidewalls of the first electrode; and a second electrode formed on a second portion of the fin structure. The first and second portions are different. The second electrode includes a surface that is in direct contact with a surface of the spacers.
    Type: Application
    Filed: February 8, 2018
    Publication date: June 21, 2018
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10002305
    Abstract: A fisheye image display method is adapted to a display device, wherein a display screen of the display device is divided into a plurality of view cells. The fisheye image display method includes steps of receiving a fisheye image; generating an original image and a plurality of regional images according to the fisheye image, wherein the regional images are corresponding to a plurality of regions of interest in the original image; and arranging the regional images in at least two of the view cells, wherein the at least two view cells are adjacent to each other horizontally or vertically, and one of the at least two view cells includes at least two of the regional images.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: June 19, 2018
    Assignee: VIVOTEK INC.
    Inventors: Yi-Hsuen Shih, Chien-Wen Liu
  • Patent number: 10002765
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Publication number: 20180166396
    Abstract: Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.
    Type: Application
    Filed: July 3, 2017
    Publication date: June 14, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen LEE, Hsien-Wen LIU, Shin-Puu JENG
  • Patent number: 9996191
    Abstract: A panel includes a plurality of first sensing electrodes and a plurality of second sensing electrodes. At least one of the first sensing electrodes includes multiple openings. The second sensing electrodes are located in the openings, respectively. The first sensing electrodes and the second sensing electrodes form a sensing layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 12, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chi-Cheng Chen, Gui-Wen Liu
  • Patent number: 9997415
    Abstract: A semiconductor device includes a substrate, first and second metals, and a second semiconductor material. The substrate includes a first semiconductor material and has first and second substrate portions. The first metal is reacted with the first substrate portion of the substrate. The second semiconductor material is above the second substrate portion of the substrate and is different from the first semiconductor material. The second metal is reacted with the second semiconductor material.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 9986682
    Abstract: A fixed-line trimmer head for a rotary trimmer device includes the upper portion having a periphery, wherein the upper portion has a plurality of openings spaced from the periphery; and a plurality of mechanisms. Each mechanism can hold a strip of line and includes a post portion disposed through one of the openings in the upper portion, and a flange disposed at one end of the post portion and sandwiched between the upper portion and lower portion of the trimmer head to prevent vertical movement of the mechanism. The post portion includes two line channels, each line channel defining a passageway to receive the same strip of line, wherein at least one of the line channels is curved such that any portion of the strip of line being received through the passageway of that line channel is bent at that portion of the strip of line away from the second line channel while passing through that at least one line channel that is curved.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: June 5, 2018
    Assignee: Shakespeare Company, LLC
    Inventors: David B. Skinner, Wen Liu
  • Patent number: 9991388
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Publication number: 20180151566
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Application
    Filed: January 29, 2018
    Publication date: May 31, 2018
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20180151752
    Abstract: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 31, 2018
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang
  • Publication number: 20180151512
    Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.
    Type: Application
    Filed: April 12, 2017
    Publication date: May 31, 2018
    Inventors: SHIN-PUU JENG, TZU-JUI FANG, HSI-KUEI CHENG, CHIH-KANG HAN, YI-JEN LAI, HSIEN-WEN LIU, YI-JOU LIN