Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10290590
    Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Tzu-Jui Fang, Hsi-Kuei Cheng, Chih-Kang Han, Yi-Jen Lai, Hsien-Wen Liu, Yi-Jou Lin
  • Publication number: 20190133550
    Abstract: An ultrasound imaging system is configured to interface with a dual frequency ultrasound transducer having one or more low frequency ultrasound arrays and one or more high frequency ultrasound arrays. The imaging system produces driving pulses for both the high frequency ultrasound array and the low frequency ultrasound imaging array. Analog echo signals are processed to produce a low frequency ultrasound image and a high frequency ultrasound image that are simultaneously displayed. Tissue shown in the high frequency ultrasound image is a portion of the tissue shown in the low frequency ultrasound image.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Inventors: Kai Wen Liu, Nicholas Christopher Chaggares
  • Publication number: 20190140070
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20190139829
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 9, 2019
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20190133557
    Abstract: An ultrasound imaging system is configured to interface with a dual frequency ultrasound transducer having one or more low frequency ultrasound arrays and one or more high frequency ultrasound arrays. The imaging system produces driving pulses for both the high frequency ultrasound array and the low frequency ultrasound imaging array. Analog echo signals are processed to produce a low frequency ultrasound image and a high frequency ultrasound image that are simultaneously displayed. Tissue shown in the high frequency ultrasound image is a portion of the tissue shown in the low frequency ultrasound image.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Inventors: Kai Wen Liu, Nicholas Christopher Chaggares
  • Patent number: 10282012
    Abstract: A touch display panel includes a first substrate, a second substrate, a display medium layer, a transparent electrode layer, a first conductive layer, a control unit and a ground electrode layer. The display medium layer is disposed between the first and second substrates. The transparent electrode layer is disposed on an inner surface of the first substrate and includes touch electrodes disposed in the display region. The first conductive layer is disposed at the transparent electrode layer and includes touch conductive lines and force sensing lines. Each touch conductive line is electrically connected to one touch electrode. The force sensing lines are electrically insulated from the touch conductive lines. A portion of the force sensing lines is connected to the control unit. The ground electrode layer is disposed on the second substrate. A force sensor is formed of the ground electrode layer, the force sensing lines and the control unit.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 7, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chi-Cheng Chen, Gui-Wen Liu
  • Patent number: 10283613
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; a fin structure including one or more fins formed on the semiconductor substrate; an insulator material formed between each of the one or more fins; a dielectric layer formed on a first portion of the fin structure; a first electrode formed on the dielectric layer; spacers formed on sidewalls of the first electrode; and a second electrode formed on a second portion of the fin structure. The first and second portions are different. The second electrode includes a surface that is in direct contact with a surface of the spacers.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10283590
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20190131178
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 2, 2019
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20190131294
    Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 2, 2019
    Inventors: Fang-Wen LIU, Tseng-Fu LU, Wei-Ming LIAO
  • Publication number: 20190131274
    Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: Zhi-Qiang WU, Chun-Fu CHENG, Chung-Cheng WU, Yi-Han WANG, Chia-Wen LIU
  • Publication number: 20190131273
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 10276437
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Patent number: 10276228
    Abstract: A dynamic random access memory (DRAM) DRAM includes a memory array, a temperature sensor and a control device. The temperature sensor is configured to sense a temperature of the DRAM. The control device is configured to adjust a sense frequency based on a retention ability of the memory array, and to activate the temperature sensor according to the adjusted sense frequency.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 30, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10276448
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Patent number: 10276664
    Abstract: A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Jean-Pierre Colinge
  • Publication number: 20190123042
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20190123143
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 25, 2019
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Publication number: 20190123177
    Abstract: A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20190122071
    Abstract: Techniques are described that facilitate automatically distinguishing between different expressions of a same or similar emotion. In one embodiment, a computer-implemented is provided that comprises partitioning, by a device operatively coupled to a processor, a data set comprising facial expression data into different clusters of the facial expression data based on one or more distinguishing features respectively associated with the different clusters, wherein the facial expression data reflects facial expressions respectively expressed by people. The computer-implemented method can further comprise performing, by the device, a multi-task learning process to determine a final number of the different clusters for the data set using a multi-task learning process that is dependent on an output of an emotion classification model that classifies emotion types respectively associated with the facial expressions.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 25, 2019
    Inventors: Feng Jin, Wen Liu, Yong Qin, Qin Shi, Peng Wang, Shi Lei Zhang