Abstract: A positioning structure for a clutch of an engine of a remote control model contains: a flywheel, multiple connection parts, multiple torsion springs, and multiple limitation elements. The flywheel includes a fitting element, a nut, and multiple fixing posts. Each of the multiple connection parts includes two opposites through orifices, an accommodation chamber, an abutting portion, and a recess. Each of the multiple torsion springs has a first central hole, a first contact segment, and a second contact segment. Each of the multiple limitation elements is rotatably fixed between each fixing post of the flywheel and the first central hole of each torsion spring, wherein each limitation element includes a support portion concentric with each fixing post, and the support portion has a second central hole rotatably fitted with each fixing post and has an external fence contacting with the first central hole.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration.

Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.

Abstract: Techniques are described that facilitate automatically distinguishing between different expressions of a same or similar emotion. In one embodiment, a computer-implemented is provided that comprises partitioning, by a device operatively coupled to a processor, a data set comprising facial expression data into different clusters of the facial expression data based on one or more distinguishing features respectively associated with the different clusters, wherein the facial expression data reflects facial expressions respectively expressed by people. The computer-implemented method can further comprise performing, by the device, a multi-task learning process to determine a final number of the different clusters for the data set using a multi-task learning process that is dependent on an output of an emotion classification model that classifies emotion types respectively associated with the facial expressions.

Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.

Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Abstract: A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.

Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit, an accessing device and a refresh device. The refresh unit has a plurality of memory rows. The accessing device is configured to access the memory rows. The refresh device is configured to refresh the refresh unit in a first manner in response to a first event, in which a quantity of accessed memory rows of the refresh unit is not greater than a threshold quantity. The refresh device is configured to refresh the refresh unit in a second manner in response to a second event, in which the quantity of accessed memory rows of the refresh unit is greater than the threshold quantity.

Abstract: Asphalt emulsions, methods of forming asphalt emulsions, and composite pavement structures formed from the asphalt emulsions are provided herein. In an embodiment, an asphalt emulsion includes a base asphalt component, water, and an oxidized high density polyethylene. The base asphalt component is present in an amount of from about 15 to about 70 weight %, the water is present in an amount of at least about 25 weight %, and the oxidized high density polyethylene is present in an amount of from about 1 to about 20 weight %, where all amounts are based on the total weight of the asphalt emulsion. The oxidized high density polyethylene has an acid value of from about 5 to about 50 mgKOH/g. The asphalt emulsion is free of aggregate and other mineral materials.