Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180047662
    Abstract: A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming, on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 15, 2018
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chih-Wen Liu
  • 3D capacitor and method of manufacturing same
    Patent number: 9893163
    Abstract: A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Multi-Fin device and method of making same
    Patent number: 9893061
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • HINGE MECHANISM, ELECTRONIC DEVICE AND METHOD CAPABLE OF AUTOMATICALLY EXECUTING ANGLE ROTATION
    Publication number: 20180039250
    Abstract: An electronic device has a method capable of automatically executing angle rotation. A second body is rotatably connected to a first body of the electronic device. A hinge mechanism is disposed between the first body and the second body. The hinge mechanism includes a hinge component, a motor unit, a coupling component and an angle detecting unit. The first body and the second body are connected to the hinge component. The motor unit is electrically connected to a controller of the electronic device. The coupling component is connected between the hinge component and the motor unit. The angle detecting unit is connected to the hinge component or the coupling component to read its rotary angle. The controller drives the motor unit to rotate the hinge component via the coupling component, and the second body can be moved relative to the first body and be fixed at a predetermined position.
    Type: Application
    Filed: January 23, 2017
    Publication date: February 8, 2018
    Inventors: Chen-Yi Liang, Cheng-Wei Chang, Che-Wen Liu
  • FINFET Structure and Method for Fabricating the Same
    Publication number: 20180040720
    Abstract: A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor material, growing a second semiconductor material in the trench to form a middle portion of the fin, forming a first carbon doped layer over the middle portion of the fin, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin, replacing outer portions of the upper portion of the fin with a second carbon doped layer and drain/source regions, wherein the first carbon doped layer and the second carbon doped layer are separated by the upper portion of the fin and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • FINFETS with Wrap-Around Silicide and Method Forming the Same
    Publication number: 20180040738
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 8, 2018
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • FinFETs and methods for forming the same
    Patent number: 9887274
    Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • FinFET devices and methods of forming
    Patent number: 9887137
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • FIXATION IDENTIFICATION USING DENSITY OPTIMIZATION
    Publication number: 20180032816
    Abstract: A fixation identification system includes an eye-tracking device and a fixation identification device disposed in electrical communication with the eye-tracking device. The fixation identification device includes a controller having a memory and a processor, the controller being configured to identify each gaze position data element received from the eye-tracking device as one of fixation gaze position data and saccade gaze position data, each gaze position data element corresponding to a visual location associated with a field of view at a corresponding time; identify at least one fixation region associated with the fixation gaze position data; adjust a number of fixation gaze position data elements associated with the at least one fixation region; and generate a density optimized fixation region based upon the adjusted number of fixation gaze position data elements.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 1, 2018
    Inventors: Andrew C. Trapp, Soussan Djamasbi, Wen Liu
  • USING METAL-CONTAINING LAYER TO REDUCE CARRIER SHOCK IN PACKAGE FORMATION
    Publication number: 20180033782
    Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Yi-Jou Lin
  • Integrated fan-out package on package structure and methods of forming same
    Patent number: 9881908
    Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Hsien-Wen Liu, Po-Yao Lin, Cheng-Lin Huang, Shyue-Ter Leu, Shin-Puu Jeng
  • Electrostatic discharge protection solutions
    Patent number: 9882377
    Abstract: Electrostatic discharge protection circuits and methods for protecting a core circuit from an electrostatic discharge event. The protection circuit may include a first anti-parallel diode pair including a first terminal coupled to an input/output pad, and a second anti-parallel diode pair including a second terminal coupled to a negative power supply voltage. The second anti-parallel diode pair is coupled in series with the first anti-parallel diode pair at a node. An offset pad is coupled to the node. The offset pad is configured to receive a first signal that is a duplicate of a second signal that is received at the input/output pad.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Giuseppe La Rosa, You Li, Wen Liu
  • HVAC module with anti-backflow control and method of operation
    Patent number: 9879870
    Abstract: HVAC module has an air inlet, an evaporator downstream of the blower and a heater downstream of the evaporator, and a rear mixing zone downstream of the evaporator and the heater, wherein a control valve prevents cold air from flowing back towards the hot air by regulating the pressure of the cold air. A method is devised to control anti-backflow control valve of such an HVAC module by the steps of reading pressure and temperatures at various points in the HVAC module; setting air flow and temperature discharge targets; calculating the resistance of the control valve and a bland valve; determining corresponding control valve and blend valve positions; and moving the control valve and blend valve to those corresponding positions.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: January 30, 2018
    Assignee: MAHLE International GmbH
    Inventors: Mingyu Wang, Yanping Xia, Wen Liu, Prasad S. Kadle, Jeffrey C. Kinmartin
  • FETS and Methods of Forming FETS
    Publication number: 20180026038
    Abstract: A method includes forming a first semiconductor strip on a substrate, the first semiconductor strip including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. A first portion of the first crystalline semiconductor material in first semiconductor strip is converted to a dielectric material, where a second portion of the first crystalline semiconductor material remains unconverted. Gate structures are formed over the first semiconductor strip and source/drain regions are formed on opposing sides of the gate structures.
    Type: Application
    Filed: August 14, 2017
    Publication date: January 25, 2018
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Chih-Hao Wang
  • Wrap around silicide for FinFETs
    Patent number: 9876108
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20180019326
    Abstract: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Fang-Liang LU, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG
  • Field-Effect Transistors Having Contacts To 2D Material Active Region
    Publication number: 20180012962
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 11, 2018
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
    Publication number: 20180012807
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Application
    Filed: September 1, 2017
    Publication date: January 11, 2018
    Inventors: I-Wen WU, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Isolation Structure of Fin Field Effect Transistor
    Publication number: 20180012977
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • METALLIC CHANNEL DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180013012
    Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Inventors: Miin-Jang CHEN, Chi-Wen LIU, Po-Hsien CHENG