Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of controlling the discharge of temperature-conditioned air
    Patent number: 9776471
    Abstract: HVAC unit has a single blower fan, an evaporator downstream of the blower and a heater downstream of the evaporator, wherein each zone outlet includes a temperature mixing door for controlling portions of hot and cold air and an output valve for controlling a zonal output flow rate. A method is devised to control the discharge of temperature-conditioned air from a plurality of zone outlets of an automotive HVAC system via such an HVAC unit by the steps of reading an operator-requested zonal discharge blower level for each of the zone outlets; converting each zonal discharge blower level request to a zonal flowrate request; calculating a total requested output flowrate as a summation of all zonal flowrate requests; and adjusting a blower voltage to a minimum voltage required for generating the total requested output flowrate.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 3, 2017
    Assignee: MAHLE International GmbH
    Inventors: Wen Liu, Mingyu Wang, Yanping Xia, Prasad S. Kadle, Jeffrey C. Kinmartin
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
    Publication number: 20170278968
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm? or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Application
    Filed: September 27, 2016
    Publication date: September 28, 2017
    Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
  • Semiconductor Device with Self-Aligned Contact
    Publication number: 20170278751
    Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Chao-Hsun Wang, Shih-Wen Liu, Fu-Kai Yang, Hsien-Cheng Wang, Mei-Yun Wang
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170278962
    Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.
    Type: Application
    Filed: July 20, 2016
    Publication date: September 28, 2017
    Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20170278971
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • FETs and methods of forming FETs
    Patent number: 9773786
    Abstract: An embodiment is a method including forming a first fin and a second fin on a substrate, the first fin and the second fin each including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. Converting the first crystalline semiconductor material in the second fin to a dielectric material, wherein after the converting step, at least a portion of the first crystalline semiconductor material in the first fin remains unconverted. Forming gate structures over the first fin and the second fin, and forming source/drain regions on opposing sides of the gate structures.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Chih-Hao Wang
  • Isolation structure of fin field effect transistor
    Patent number: 9773892
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Method for fabricating a fine structure
    Patent number: 9773662
    Abstract: In a method for fabricating a fine structure, a metal oxide layer is formed by using an atomic layer deposition over a substrate, and the metal oxide layer is removed. An interfacial oxide layer is formed between the metal oxide layer and the substrate. The interfacial oxide layer is an oxide of an element constituting the substrate, and the interfacial oxide layer is removed.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: September 26, 2017
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Po-Hsien Cheng
  • Method of Fabricating a Semiconductor Device Having Modified Profile Metal Gate
    Publication number: 20170271469
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Yu-Lien Huang, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Process design to improve transistor variations and performance
    Patent number: 9768297
    Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
  • LIGHT SOURCE MODULE AND DISPLAY APPARATUS
    Publication number: 20170261672
    Abstract: A light source module including a first light guide plate, a first light source, a second light guide plate, a second light source, and a turning film is provided. The first light guide plate and the second light guide plate are sequentially stacked up. The second light guide plate is disposed between the first light guide plate and the turning film. The turning film has a plurality of prism columns, the prism columns face the second light guide plate. The first light guide plate includes a first light exiting surface, the first light exiting surface is located at a side facing the turning film and has a plurality of lenticular lens structures. The lenticular lens structures are arranged along a first direction and extended along a second direction perpendicular to the first direction. Besides, a display apparatus is also provided.
    Type: Application
    Filed: March 3, 2017
    Publication date: September 14, 2017
    Applicant: Young Lighting Technology Inc.
    Inventors: Kuan-Wen Liu, Chi-Lung Lee, Hao-Jan Kuo
  • Gate contact structure of FinFET
    Patent number: 9761677
    Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Asymmetric Application of Pressure to a Wafer During a CMP Process
    Publication number: 20170256414
    Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.
    Type: Application
    Filed: March 2, 2016
    Publication date: September 7, 2017
    Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
  • FISHEYE IMAGE DISPLAY METHOD
    Publication number: 20170255836
    Abstract: A fisheye image display method is adapted to a display device, wherein a display screen of the display device is divided into a plurality of view cells. The fisheye image display method includes steps of receiving a fisheye image; generating an original image and a plurality of regional images according to the fisheye image, wherein the regional images are corresponding to a plurality of regions of interest in the original image; and arranging the regional images in at least two of the view cells, wherein the at least two view cells are adjacent to each other horizontally or vertically, and one of the at least two view cells includes at least two of the regional images.
    Type: Application
    Filed: March 5, 2017
    Publication date: September 7, 2017
    Inventors: Yi-Hsuen Shih, Chien-Wen Liu
  • Semiconductor arrangement and formation thereof
    Patent number: 9754838
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • FinFET with dummy gate on non-recessed shallow trench isolation (STI)
    Patent number: 9754842
    Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • FinFETs with strained well regions
    Patent number: 9748142
    Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu
  • Method, system and electronic apparatus for searching nearby apparatus
    Patent number: 9749943
    Abstract: A method, a system and an electronic apparatus for searching nearby apparatuses are proposed. The method includes: searching at least one first apparatus belonging to a first subnet which the electronic apparatus belongs to, and accordingly generating a first list; scanning at least one access point (AP) near the electronic apparatus, and accordingly generating a first AP list; uploading the first AP list to a server, and receiving a second list from the server, where the second list includes at least one second apparatus, and a similarity between a second AP list of each second apparatus and the first AP list is higher than a predetermined threshold; and uniting the first list and the second list to generate a pairing list including at least one apparatus to be paired.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: August 29, 2017
    Assignee: Acer Incorporated
    Inventors: Po-Hsiang Wang, Yi-Wen Liu, Hao-Ting Chang, Wen-Ping Chang
  • Semiconductor Device and Method of Forming the Same
    Publication number: 20170243976
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Hsin-Chieh Huang, Cheng-Chien Li
  • ULTRASOUND TRANSDUCER WITH DATA COMPRESSION
    Publication number: 20170242112
    Abstract: A transducer for an ultrasound imaging system includes an array of transducer elements and an analog-to-digital converter configured to convert analog signals produced by the transducer elements into corresponding digital samples that are encoded with a first number of bits. One or more memories are used to store digital samples associated with frames of ultrasound data. A processor or logic circuit in the transducer is configured to compress the digital ultrasound data by calculating differences between the samples and encoding the differences with a second number of bits that is less than the first number of bits. In addition, the logic circuit is configured to transmit a packet that includes the differences encoded with the second number of bits and an overflow portion that encodes the differences that are too large to be encoded with the second number of bits.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventor: Kai Wen Liu