Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9836075
    Abstract: A voltage detector operates to detect a system power supply voltage and generate a trigger signal. A control signal generator responds to the trigger signal and generates a control signal. A DC bias generator responds to the control signal by generating a DC bias. The control signal controls the DC bias to have a first value when the power supply voltage is a first voltage and have a second value when the power supply voltage is a second voltage different from the first voltage, wherein the first value is different from the second value. A dynamic DC bias is generated which can not only support a larger voltage scope, but also significantly improves signal to noise ratio. The system power supply detection may concern stop/start operation of an automobile engine.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Min Chen, Wen Liu, Hong Xia Li
  • Publication number: 20170345944
    Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xian-Rui Chang
  • Patent number: 9831165
    Abstract: A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: November 28, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chih-Wen Liu
  • Patent number: 9824831
    Abstract: A detachable keyswitch mechanism includes a base and a keyswitch. The base includes a bottom plate and a lateral plate bent from the bottom plate. The base further includes an opening structure disposed on the lateral plate, a first rotating portion disposed between the bottom plate and the lateral plate, and a constraining portion disposed on the bottom plate. The keyswitch includes a body rotatably disposed inside the opening structure, a second rotating portion disposed on an upper side of the body and pivotably connected to the first rotating portion, a recovering portion connected to a low side of the body, and an actuating portion disposed on a surface of the body. An end of the recovering portion opposite to the body contacts against the constraining portion. The actuating portion is adapted to actuate a switch disposed on the base when the keyswitch rotates relative to the base.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: November 21, 2017
    Assignee: Wistron Corporation
    Inventors: Yu-Ju Liu, Che-Wen Liu
  • Publication number: 20170330959
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 9818878
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Publication number: 20170323943
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Patent number: 9812395
    Abstract: A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a first connection region to a second connection region defined thereon; performing anodic oxidation on the substrate having the protruding structure; forming one or more nanowire interconnect in the protruding structure traversing between the first connection region and the second connection region; the nanowire interconnect being surrounded by a dielectric layer formed during the anodic oxidation.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20170313668
    Abstract: Provided herein are methods and compositions related to a retinoid receptor-selective pathway. As described herein, this pathway can be targeted to manipulate a tumor microenviroment. For example, the methods and compositions described herein can be used to induce apoptosis in a cancer cell. Further, the compositions described herein, including Sulindac and analogs thereof, can be used to target this pathway for the treatment or prevention of cancer in human patients.
    Type: Application
    Filed: February 16, 2017
    Publication date: November 2, 2017
    Inventors: Xiao-kun ZHANG, Ying SU, Hu ZHOU, Wen LIU, Pei-Qiang HUANG
  • Publication number: 20170317181
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Che-Wei YANG, Chi-Wen LIU, Hao-Hsiung LIN, Ling-Yen YEH
  • Publication number: 20170317182
    Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.
    Type: Application
    Filed: September 1, 2016
    Publication date: November 2, 2017
    Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
  • Patent number: 9806178
    Abstract: A method comprises recessing a substrate to form a fin enclosed by an isolation region, wherein the substrate is formed of a first semiconductor material, recessing the fin to form a trench over a lower portion of the fin, growing a second semiconductor material in the trench to form a middle portion of the fin through a first epitaxial process, forming a first carbon doped layer over the lower portion through a second epitaxial process, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin through a third epitaxial process, forming a first source/drain region through a fourth epitaxial process, wherein a second carbon doped layer is formed underlying the first source/drain region and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9806076
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20170304924
    Abstract: A new electrospark deposition (ESD) method and related system are provided in the present invention based on the use of a magnetized electrode, namely magnetic-aided ESD (M-ESD). In particular, the present invention uses a magnetized electrode (either magnetized by an electro-magnet or being a permanent magnet) to attract fine coating powders at the tip thereof which acts as a soft brush to coat on intricate surface profiles. Accordingly, the method of the present invention is able to provide a soft contact between the magnetized anode and the workpiece to be coated or manipulated. The present invention is useful in various surface engineering applications in the fields of aeronautical (e.g. restoration and repair of damaged aircraft turbine blades), nuclear reactors, military engineering, and in medical industries.
    Type: Application
    Filed: April 20, 2016
    Publication date: October 26, 2017
    Inventors: Jiang Wen LIU, Tai Man YUE, Zhichao LIU
  • Patent number: 9796071
    Abstract: The present invention relates to a spring reset device for a piston mechanism. In certain embodiments, the spring reset device includes: a connecting plate, a pull rod, a plurality of reset springs, and a plurality of brackets. The connecting plate has a plurality of connecting pins. Each of the reset springs has a first end, and a second end. Each of the brackets has a connecting pin. The spring reset device is positioned on a top end of a piston body. The piston body includes a piston cylinder body, a piston plate, a piston rod, and a cylinder cover. A lower side of the piston plate is connected to the piston rod through a thread. First end of each of reset springs is rotatably connected to a hook portion of connecting plate. Second end of each of reset springs is rotatably connected a hook portion of a corresponding bracket.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: October 24, 2017
    Assignee: TAIZHOU DAJIANG IND. CO., LTD.
    Inventors: Gui-Wen Liu, Ming-Jun Yang, Jin-Quan Huang
  • Patent number: 9792531
    Abstract: Intelligent multi-scale image parsing determines the optimal size of each observation by an artificial agent at a given point in time while searching for the anatomical landmark. The artificial agent begins searching image data with a coarse field-of-view and iteratively decreases the field-of-view to locate the anatomical landmark. After searching at a coarse field-of view, the artificial agent increases resolution to a finer field-of-view to analyze context and appearance factors to converge on the anatomical landmark. The artificial agent determines applicable context and appearance factors at each effective scale.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 17, 2017
    Assignee: Siemens Healthcare GmbH
    Inventors: Bogdan Georgescu, Florin Cristian Ghesu, Yefeng Zheng, Dominik Neumann, Tommaso Mansi, Dorin Comaniciu, Wen Liu, Shaohua Kevin Zhou
  • Publication number: 20170293725
    Abstract: A computer-implemented method for predicting answers to questions concerning medical image analytics reports includes splitting a medical image analytics report into a plurality of sentences and generating a plurality of sentence embedding vectors by applying a natural language processing framework to the plurality of sentences. A question related to subject matter included in the medical image analytics report is received and a question embedding vector is generated by applying the natural language processing framework to the question. A subset of the sentence embedding vectors most similar to the question embedding vector is identified by applying a similarity matching process to the sentence embedding vectors and the question embedding vector. A trained recurrent neural network (RNN) is used to determine a predicted answer to the question based on the subset of the sentence embedding vectors.
    Type: Application
    Filed: March 10, 2017
    Publication date: October 12, 2017
    Inventors: Wen Liu, Ashutosh Modi, Bogdan Georgescu, Francisco Pereira
  • Publication number: 20170294499
    Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.
    Type: Application
    Filed: September 16, 2016
    Publication date: October 12, 2017
    Inventors: Chang Ming Lu, Chia-Yu Chen, Chih Pang Chang, Ching-Sang Chuang, Hung-Che Ting, Jung Yen Huang, Sheng Hui Shen, Shih Chang Chang, Tsung-Hsiang Shih, Yu-Wen Liu, Yu Hung Chen, Kai-Chieh Wu, Lun Tsai, Takahide Ishii, Chung-Wang Lee, Hsing-Chuan Wang, Chin Wei Hsu, Fu-Yu Teng
  • Patent number: 9786774
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain region; and a metal gate surrounding a portion the channel region, wherein the metal gate comprising a first gate portion adjacent to the source region having a first thickness and a second gate portion adjacent to the drain region having a second thickness less than the first thickness.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Chi-Wen Liu
  • Patent number: 9777725
    Abstract: The invention relates to a high pressure water pump and a steam powered nailing gun having the high pressure water pump. In certain embodiments, high pressure water pump includes: an upper pump body, a lower pump body, a water discharge valve, a water intake valve, a plunger, a guide sleeve, a hammering cap, an adjustment knob, and an evacuation valve. Both upper and lower pump body are connected by connecting bolts. A sealing ring is disposed between upper and lower pump body and a sealing element is disposed between the upper pump body and plunger. Plunger is sheathed in upper pump body. The hammering cap is threadedly connected to the plunger. The adjustment knob is connected to an upper end of upper pump body. The hammering cap is moveably connected to the adjustment knob through the plunger. A plunger reset spring is disposed between hammering cap and adjustment knob.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: October 3, 2017
    Assignee: TAIZHOU DAJIANG IND. CO., LTD.
    Inventors: Gui-Wen Liu, Ming-Jun Yang, Jin-Quan Huang