Abstract: A trimmer head having at least two pivoting line holders for holding multiple folded strips of trimming line is presented wherein said pivoting line holders are retained within said housing between said housing and said cover and extend upward through apertures in said cover, said line holders being capable of movement around a vertical axis of rotation, at least three embodiments are disclosed which provide a rounded landing for supporting the inner radius of a folded strip of trimming line, the rounded geometry of the landing prevents line stress and breakage, the various embodiments include a pivot post having two parallel straight through holes with a rounded vertical wall between the through holes, a single open passageway having a center metal post, and a single open passageway having a series of at least two metal pins through the center of the passageway.

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

Abstract: A representative method for fabricating a field effect transistor comprises forming a source region and a drain region disposed in a substrate; forming a gate structure over the substrate, the gate structure comprising sidewalls and a top surface, the gate structure interposing the source region and the drain region; forming a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; forming an interlayer dielectric layer over the CESL; forming a gate contact extending through the interlayer dielectric layer; and forming a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm.

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration.

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.

Abstract: A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

Abstract: A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved.

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

Abstract: An electronic device includes a transistor having a body and a body biasing circuit. The body biasing circuit includes a threshold estimator circuit to estimate a threshold voltage of the transistor and a comparison circuit to compare the threshold voltage of the transistor to a reference threshold voltage and to generate a comparison signal based thereupon. A bias adjust circuit generates a body biasing voltage that biases the body of the transistor as a function of the comparison signal, the body biasing voltage being a voltage that, when applied to the body of the transistor, adjusts the threshold voltage thereof to be equal to the reference threshold voltage.

Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

Abstract: A method, a system and an electronic apparatus for searching nearby apparatuses are proposed. The method includes: searching at least one first apparatus belonging to a first subnet which the electronic apparatus belongs to, and accordingly generating a first list; scanning at least one access point (AP) near the electronic apparatus, and accordingly generating a first AP list; uploading the first AP list to a server, and receiving a second list from the server, where the second list includes at least one second apparatus, and a similarity between a second AP list of each second apparatus and the first AP list is higher than a predetermined threshold; and uniting the first list and the second list to generate a pairing list including at least one apparatus to be paired.

Abstract: A video file playback system capable of previewing an image, a method thereof, and a computer program product can sequentially compare change amounts between chronological two of frame images, select the frame images, of which the change amounts exceed a preset value, in at least one time interval, and select a frame image, which has a maximum change amount, in the frame images in each time interval as a preview image. By displaying a preview image corresponding to each time interval, a user can quickly browse key images of each time interval.

Abstract: A pre-selectable video file playback system and method, and a computer program product are provided. Multiple first images are captured from multiple frame images in a first time interval, and two chronological first images thereafter are compared sequentially. A next first image is selected if the next first image is substantially different from a previous first image, and the next first image is not selected if the next first image is substantially the same as the previous first image. By displaying the selected first images, the number of images that users watch may be reduced.

Abstract: A method, a system and an electronic apparatus for searching nearby apparatuses are proposed. The method includes: searching at least one first apparatus belonging to a first subnet which the electronic apparatus belongs to, and accordingly generating a first list; scanning at least one access point (AP) near the electronic apparatus, and accordingly generating a first AP list; uploading the first AP list to a server, and receiving a second list from the server, where the second list includes at least one second apparatus, and a similarity between a second AP list of each second apparatus and the first AP list is higher than a predeteiuiined threshold; and uniting the first list and the second list to generate a pairing list including at least one apparatus to be paired.

Abstract: A transmission device, a receiving device and a method of sharing data are provided. The transmission device includes a touch-display module which includes one or a plurality of display areas, wherein each of the display areas displays a respective display result corresponding to the same or different applications; a link module which is configured to establish a touch link with one or a plurality of receiving devices through the touch-display module; a judgment module which is configured to determine the display area which the receiving device is in physical proximity to, to generate the judgment information; a management module which is configured to generate application information according to the judgment information; and a sending module, configured to transmit the application information to the receiving device through the touch-display module.

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.