Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

Abstract: A device comprising a first plate disposed on top of a second plate where the first and second plates are parallel and separated by a fixed distance with a spacer, and wherein the spacer fits around the perimeter of the first and second plates creating a void space, and wherein the second plate has a plurality of pin-sized holes, and wherein a pump sits in the void space and is operably coupled to the plates, wherein the plates are operably coupled to the bottom, exterior hull of an Unmanned Underwater Vehicle (UUV), and wherein the pump is configured to pump liquid into the void space between the parallel plates.

Abstract: A method of analyzing biological particles for a biological particle analyzer includes outputting a first detection result when at least one particle has arrived at the first detection area, outputting a second detection result to the control module when the particles have arrived at the second detection area, and determining when to turn on or off the light emission source and outputting a control signal to turn on or off the light emission source according to the first detection result, wherein a control module is configured to calculate a turn-on time according to different particle characteristics and an average velocity of the at least one particle, and the light emission source is turned on only when the at least one particle is being tested during the turn-on time.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a vertical transistor device. The integrated chip may have a semiconductor body with a trench extending along first sides of a source region, a channel region over the source region, and a drain region over the channel region. A gate electrode is arranged along a first sidewall of the trench, and a metal contact is arranged on the drain region. An isolation dielectric material is disposed within the trench. The isolation dielectric material is vertically over a top surface of the gate electrode and is laterally adjacent to the gate electrode.

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: Provided is a method for fabricating a memory device including forming a stack layer on a substrate, and embedding a plurality of gate pillar structures and a plurality of dielectric pillars in the stack layer. The plurality of gate pillar structures and the plurality of dielectric pillars extend along a same direction and are alternately arranged, so that the stack layer is divided into a plurality of stack structures.

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions are present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.

Abstract: A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer. The recessing forms a trench disposed between sidewall portions of the spacer layer. At least a portion of the sacrificial layer is removed, and a source/drain region is formed in the trench.

Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: A shave ice device having a first compartment, a second compartment below the first compartment, a gripping mechanism for gripping a block of ice, a rotating mechanism for rotating the gripping mechanism, a shaving plate separating the first compartment from the second compartment, and a cooling mechanism in communication with the first compartment. The cooling mechanism maintains the temperature of the first compartment at about 0 degrees Celsius or lower.

Abstract: An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner layers. Each interconnect line is positioned within a trench. At least one first liner layer is affixed between the trench bottom surface and the interconnect bottom surface. The interconnect structure further includes one or more second liner layers. At least one of the second liner layers is affixed directly to the interconnect top surface and at least one interconnect side surface. The interconnect structure further includes at least one air gap. Each air gap is positioned between the trench side surface and the interconnect side surface. A corresponding method of manufacture and product of a method of manufacture are also disclosed.

Abstract: Intelligent image parsing for anatomical landmarks and/or organs detection and/or segmentation is provided. A state space of an artificial agent is specified for discrete portions of a test image. A set of actions is determined, each specifying a possible change in a parametric space with respect to the test image. A reward system is established based on applying each action of the set of actions and based on at least one target state. The artificial agent learns an optimal action-value function approximator specifying the behavior of the artificial agent to maximize a cumulative future reward value of the reward system. The behavior of the artificial agent is a sequence of actions moving the agent towards at least one target state. The learned artificial agent is applied on a test image to automatically parse image content.

Abstract: A method for managing virtual control interface of an electronic device, and an associated apparatus and an associated computer program product are provided, where the method includes: utilizing a specific set of common user interfaces (UIs) as a common service for a plurality of applications, wherein the specific set of common UIs is a set of virtual control interfaces to be displayed on a screen, and the specific set of common UIs is provided by a system framework running on the electronic device, rather than being provided by any of the plurality of applications; and displaying the specific set of common UIs to allow a user to control the electronic device through the specific set of common UIs. The method may further include: selecting the specific set of common UIs from a plurality of sets of common UIs.

Abstract: An electronic device includes a transistor having a body and a body biasing circuit. The body biasing circuit includes a threshold estimator circuit to estimate a threshold voltage of the transistor and a comparison circuit to compare the threshold voltage of the transistor to a reference threshold voltage and to generate a comparison signal based thereupon. A bias adjust circuit generates a body biasing voltage that biases the body of the transistor as a function of the comparison signal, the body biasing voltage being a voltage that, when applied to the body of the transistor, adjusts the threshold voltage thereof to be equal to the reference threshold voltage.

Abstract: In an approach for visual liveness detection, a video-audio signal related to a speaker speaking a text is obtained. The video-audio signal is split into a video signal which records images of the speaker and an audio signal which records a speech spoken by the speaker. Then a first sequence indicating visual mouth openness is obtained from the video signal, and a second sequence indicating acoustic mouth openness is obtained based on the text and the audio signal. Synchrony between the first and second sequences is measured, and the liveness of the speaker is determined based on the synchrony.

Abstract: A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a drain region. The semiconductor structure further comprises a metal gate that surrounds a portion of the vertical channel structure. The metal gate has a gate length. The metal gate has a first gate section with a first workfunction and a first thickness. The metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness level is different from the second thickness level and the sum of the first thickness level and the second thickness level is equal to the gate length. The ratio of the first thickness level to the second thickness level for the gate length was chosen to achieve a threshold voltage level for the semiconductor device.

Abstract: A method and an apparatus for interacting with a notification are provided. The method is adapted for an end apparatus to interact with a notification provided by a communication apparatus, in which the end apparatus and the communication apparatus are connected with each other. In the method, the notification provided by the communication apparatus is received and displayed. Next, a selection operation for the notification is received, and whether a content of the notification contains an executable intent is determined. If the intent is contained, the communication apparatus is triggered to execute the intent, and whether a screen activity of the communication apparatus is triggered by the execution of the intent is determined. If the execution of the intent triggers the screen activity, a result of executing the intent is displayed.