Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: A fin structure on a substrate can have a lower portion formed from the substrate, a middle portion, and an upper portion. The middle portion can include a dielectric region having a dielectric composition and a concentrated region of a first material. The first material can be an element of the dielectric composition. The concentrated region can be located at an interface of the middle portion and lower portion. The structure can also include isolation regions in the substrate on opposing sides of the fin. The structure can also include a gate structure over the upper portion of the fin that are exposed from the isolation regions. The gate structure can include a gate dielectric and gate material over the gate dielectric. The structure can also include source/drain regions extending laterally from the upper portion and the middle portion of the fin.

Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Abstract: A device comprises a substrate comprising silicon, a fin structure comprising a lower portion formed of silicon and enclosed by an isolation region, a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer, an upper portion formed of silicon, wherein the upper portion comprises a channel and a silicon-carbon layer formed between the middle portion and the upper portion, a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region and a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.

Abstract: An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner layers. Each interconnect line is positioned within a trench. At least one first liner layer is affixed between the trench bottom surface and the interconnect bottom surface. The interconnect structure further includes one or more second liner layers. At least one of the second liner layers is affixed directly to the interconnect top surface and at least one interconnect side surface. The interconnect structure further includes at least one air gap. Each air gap is positioned between the trench side surface and the interconnect side surface. A corresponding method of manufacture and product of a method of manufacture are also disclosed.

Abstract: A method and an apparatus for interacting with a notification are provided. The method is adapted for an end apparatus to interact with a notification provided by a communication apparatus, in which the end apparatus and the communication apparatus are connected with each other. In the method, the notification provided by the communication apparatus is received and displayed. Next, a selection operation for the notification is received, and whether a content of the notification contains an executable intent is determined. If the intent is contained, the communication apparatus is triggered to execute the intent, and whether a screen activity of the communication apparatus is triggered by the execution of the intent is determined. If the execution of the intent triggers the screen activity, a result of executing the intent is displayed.

Abstract: A folding device provides a top case having magnetic elements at a top magnetic section and a bottom case having a groove and magnetic elements around the groove at a bottom magnetic section. As the top magnetic section of the top case is disposed at the bottom magnetic section of the bottom case, the top case is configurable at one of a folded position and at least two opened positions with respect to the bottom case. When the top case is at the first opened position, a first stopper and a first magnetic element at the groove of the bottom magnetic section maintain the top case at the first opened position; when the top case is at the second opened position, a second stopper and a second magnetic element at the groove of the bottom magnetic section maintain the top case at the second opened position.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A method includes providing a first source/drain contact, providing a second source/drain contact, and surrounding the first and second source/drain contacts with a dielectric material layer. The providing a first source/drain contact and the providing a second source/drain contact are performed one after the other.

Abstract: A ceiling fan lighting system includes a fan assembly, a light assembly and a lift mechanism. The fan assembly includes a motor and a plurality of fan blades being operationally coupled to the motor to permit rotation of the fan blades when the motor is supplied with power. The light assembly is coupled to the fan assembly and has at least one light source and a lamp shade enclosing the light source. Moreover, the lift mechanism is configured to move the light assembly in a vertical plane with respect to the fan assembly in order to have the lamp shade of the light assembly enclose or disclose the fan blades of the fan assembly.

Abstract: The present invention relates to voice processing and provides a method and system for correcting a text. The method comprising: determining a target text unit to be corrected in a text; receiving a reference voice segment input by the user for the target text unit; determining a reference text unit whose pronunciation is similar to a word in the target text unit based on the reference voice segment; and correcting the word in the target text unit in the text by the reference text unit. The present invention enables the user to easily correct errors in the text vocally.

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.

Abstract: An HVAC module having a reconfigurable bi-level duct system is disclosed. The air duct includes an air duct inlet in fluid communication with the HVAC module, an interior wall dividing the air duct into first and second air passageways, a bypass port enabling fluid communication between the first air and second air passageways. A downstream control valve disposed adjacent the bypass port and is configured to selectively direct air flow from one of the first and second air passageways to the other of the first and second air passageways. An upstream flow control valve is disposed adjacent to the inlet of the air duct, wherein the upstream flow control valve is configured to selectively direct air flow from the hot and cold chambers of the HVAC module to the first and second air passageways of the air duct.

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit.

Abstract: A handheld gas sensing device and sensing method thereof are provided. The handheld gas sensing device includes a plurality of gas sensing chips and a gas collector. The plurality of gas sensing chips respectively include a sensing array, a sensing interface circuit, a microcontroller, and a memory. The gas signal is determined by the gas adsorption of the sensing array. The gas signal is converted to a visible operand by using the sensing interface circuit. The visible operand is projected to a hidden operand by utilizing the calculation of Continuous Restricted Boltzmnan Machine (CRBM). The plurality of gas sensing chips are connected with each other to do the multi-layer calculation of CRBM. The probability of the to-be-detected gas is obtained. The result is recorded in the memory.

Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.