Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8546234
    Abstract: A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 1, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20130249010
    Abstract: Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Jin-Aun Ng, Ming Zhu, Chi-Wen Liu
  • Patent number: 8536056
    Abstract: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8530306
    Abstract: A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 10, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8531928
    Abstract: An optical storage apparatus and a method for automatically adjusting a loop gain thereof are provided. The method includes the following steps. Firstly, a compact disk is written by an erase power. Next, a writing state of the erase power is detected to generate an error signal. Finally, a loop gain of a servo control loop is corrected according to the error signal. Therefore, the loop gain can be corrected by the present invention according to a reflectance of the compact disk.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 10, 2013
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Yao-Wen Liu
  • Patent number: 8533638
    Abstract: A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse patterns if d?5a and c?1.5b or if 5a>d?3a and c?1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: September 10, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Kuo Kuei Fu, Yi Nan Chen, Hsien Wen Liu
  • Publication number: 20130231530
    Abstract: A magnetic maneuvering system for capsule endoscope includes the capsule endoscope, an annular fitting sleeved around the outer surface of the capsule endoscope. A plurality of magnetic driven parts are provided and distributed on the annular fitting member. The control device includes a magnetic driving part for magnetically actuating the magnetic driven parts, thus enabling the capsule endoscope to rotate and move in an organism as a result of the actuation of the magnetic driven parts. By magnetically controlling the magnetic driven parts, the capsule endoscope is allowed to rotate or move under the control of the control device to achieve better image retrieval results and improve over the poor image retrieval results obtained by the prior art since the location and direction of a traditional capsule endoscope, relying solely on the contractions of the digestive tract, cannot be controlled.
    Type: Application
    Filed: May 30, 2012
    Publication date: September 5, 2013
    Inventors: Gi-Shih Lien, Chih-Wen Liu, Joe-Air Jiang, Cheng-Long Chuang, Ming-Tsung Teng
  • Patent number: 8525262
    Abstract: The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: September 3, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20130207306
    Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.
    Type: Application
    Filed: May 31, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao Chen, Hsien-Wen Liu, Yi-Lin Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20130200141
    Abstract: The present invention discloses a biochip measuring system. The cytometer system includes a biochip and a biochip measuring apparatus. The biochip includes a substrate, for carrying bio-molecule droplet, and a stamp marking area, for receiving or displaying a stamp for identifying whether the biochip is used. The biochip measuring apparatus includes a controller, a driver circuit, a driver interface, a light, a light detector, and a stamp marking unit, for marking the stamp on the stamp marking area of the biochip after the biochip measuring apparatus completes measurement of the biochip.
    Type: Application
    Filed: August 29, 2012
    Publication date: August 8, 2013
    Inventors: Yao-Tsung Chang, Chia-Hsien Li, Ting-Wen Liu, Pai-Yang Lin
  • Publication number: 20130197384
    Abstract: A medical ventilator capable of early detecting and recognizing types of pneumonia, a gas recognition chip, and a method for recognizing gas thereof are disclosed. The gas recognition chip of the medical ventilator comprises a sensor array, a sensor interface circuit, a stochastic neural network chip, a memory and a microcontroller. The sensor array receives a plurality of multiple types of gases to produce odor signals corresponding to each type of gas. The sensor interface circuit analyzes the odor signals to produce gas pattern signals corresponding to each type of gas. The stochastic neural network chip amplifies the differences between the gas pattern signals and performs dimensional reduction on the gas pattern signals to aid the analysis. The memory stores training data. The microcontroller performs a mixed gas recognizing algorithm to early detect and recognize the type of the pneumonia according to the gas training data.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 1, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Kea-Tiong Tang, Chung-Hung Shih, Li-Chun Wang, Hsin Chen, Yi-Wen Liu, Jyuo-Min Shyu, Chia-Min Yang, Da-Jeng Yao
  • Patent number: 8497568
    Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: July 30, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Kuo Kuei Fu, Yi Nan Chen, Hsien Wen Liu
  • Patent number: 8486834
    Abstract: The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: July 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Ping Hsu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8486582
    Abstract: A surface modification to prevent oxide scale spallation is disclosed. The surface modification includes a ferritic stainless steel substrate having a modified surface. A cross-section of the modified surface exhibits a periodic morphology. The periodic morphology does not exceed a critical buckling length, which is equivalent to the length of a wave attribute observed in the cross section periodic morphology. The modified surface can be created using at least one of the following processes: shot peening, surface blasting and surface grinding. A coating can be applied to the modified surface.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: July 16, 2013
    Assignee: Battelle Memorial Institute
    Inventors: Elizabeth V. Stephens, Xin Sun, Wenning Liu, Jeffry W. Stevenson, Wayne Surdoval, Mohammad A. Khaleel
  • Patent number: 8487397
    Abstract: An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8481125
    Abstract: Molecular adsorption to the microfluidic device surfaces can be passively and actively mitigated by mixing certain hydrophilic polymers (organic polymers with repeating hydrophilic groups—the preferred polymers being amphipathic surfactants—with the sample liquid during or prior to relevant microfluidic operations. Nonionic surfactants such as polyoxyethylene sorbitan monooleate and polyoxyethylene octyl phenyl ether are especially effective. High molecular weight polyethylene polymers are also effective. The hydrophilic polymers appear to prevent binding of the fouling molecules to the microfluidic by occupying the surface sites in place of the fouling molecules or by interacting with the fouling molecules to prevent binding of the fouling molecules the surface. When surface adsorption is thus mitigated, microfluidic devices can readily handle samples containing biomolecules to enable active sample concentration, filtering, washing, transport, mixing and other sample handling operations.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: July 9, 2013
    Assignee: Advanced Liquid Logic Inc.
    Inventors: Uichong B. Yi, Peter-Patrick De Guzman, Wayne Po-Wen Liu
  • Patent number: 8476704
    Abstract: A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: July 2, 2013
    Assignee: Nan Ya Technology Corporation
    Inventors: Jeng Hsing Jang, Yi Nan Chen, Hsien Wen Liu
  • Patent number: 8476764
    Abstract: A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8470515
    Abstract: A method of forming an etch mask includes: providing a substrate having thereon a material layer to be etched; forming a hard mask layer consisting of a radiation-sensitive, single-layer resist material on the material layer; exposing the hard mask layer to actinic energy to change solvent solubility of exposed regions of the hard mask layer; and subjecting the hard mask layer to water treatment to remove the exposed regions of the hard mask layer, thereby forming a masking pattern consisting of unexposed regions of the hard mask layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: June 25, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20130157510
    Abstract: An electrical connector adapted for electrically connecting with an electronic element includes an insulating housing and a plurality of terminals. The insulating housing defines a plurality of terminal grooves penetrating through a top face thereof. A plurality of convex blocks protrudes upward and is arranged regularly on the top face of the insulating housing. The terminals are received in the terminal grooves of the insulating housing. Each terminal has a contact portion projecting upward beyond the top face of the insulating housing from the terminal grooves for contacting with the electronic element. Tops of the contact portions are further higher than a plane determined by peaks of the convex blocks to ensure the contact portions of the terminals can be pressed down by the electronic element until the convex blocks resist against the electronic element.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Applicant: PROCONN TECHNOLOGY CO., LTD.
    Inventors: Ya-Hui Hsu, Hui-Wen Liu